Source/drain regions in integrated circuit structures

Patent metadata

Field	Value
Publication number	US-12376353-B2
Application number	US-202318399885-A
Country	US
Kind code	B2
Filing date	Dec 29, 2023
Priority date	Mar 25, 2020
Publication date	Jul 29, 2025
Grant date	Jul 29, 2025

Abstract

Disclosed herein are source/drain regions in integrated circuit (IC) structures, as well as related methods and components. For example, in some embodiments, an IC structure may include: an array of channel regions, including a first channel region and an adjacent second channel region; a first source/drain region proximate to the first channel region; a second source/drain region proximate to the second channel region; and an insulating material region at least partially between the first source/drain region and the second source/drain region.

First claim

The invention claimed is:

1. An integrated circuit (IC) device, comprising:
a channel of a transistor, the channel having a first side surface and a second side surface, wherein the first side surface of the channel is opposite the second side surface of the channel;
a region of the transistor, wherein the region is either a source region or a drain region, the region has a first side surface and a second side surface, the first side surface of the region is opposite the second side surface of the region, the first side surface of the channel is aligned with the first side surface of the region, and the second side surface of the channel is aligned with the second side surface of the region;
a base region, wherein the base region includes a semiconductor material; and
an insulating material between the base region and the region.

2. The IC device of claim 1 , wherein the region is in contact with the insulating material.

3. The IC device of claim 1 , further comprising:
a die, wherein the die includes the channel and the region; and
a support, electrically coupled to the die.

4. The IC device of claim 3 , wherein the support is one of a package substrate, an interposer, or a printed circuit board.

5. The IC device of claim 3 , further comprising:
a housing around the die and the support.

6. The IC device of claim 3 , wherein the IC device is a handheld computing device or a server.

7. An integrated circuit (IC) device, comprising:
a first channel region;
a second channel region;
a first region proximate to the first channel region;
a second region proximate to the second channel region, wherein the first region is one of a source region or a drain region, and the second region is another one of the source region or the drain region; and
a further region at least partially between the first region and the second region, wherein the further region includes a first dielectric material, a second dielectric material, and a third dielectric material, wherein the first dielectric material has a U-shaped cross-section, the first dielectric material is between the second dielectric material and the first region, and the second dielectric material is between the third dielectric material and the first dielectric material.

8. The IC device of claim 7 , wherein the third dielectric material is part of a conformal layer.

9. The IC device of claim 7 , wherein the further region further includes a fourth dielectric material, and the fourth dielectric material is between the first dielectric material and a base region.

10. The IC device of claim 7 , wherein a portion of the first dielectric material is in contact with a portion of the second dielectric material.

11. The IC device of claim 10 , wherein a further portion of the first dielectric material is in contact with a portion of the third dielectric material.

12. The IC device of claim 11 , wherein the third dielectric material has a U-shaped cross-section.

13. The IC device of claim 7 , wherein the third dielectric material has a U-shaped cross-section.

14. The IC device of claim 7 , wherein the second dielectric material does not have a U-shaped cross-section.

15. An integrated circuit (IC) device, comprising:
a first channel region;
a second channel region;
a first region proximate to the first channel region;
a second region proximate to the second channel region, wherein the first region is one of a source region or a drain region, and the second region is another one of the source region or the drain region; and
a further region at least partially between the first region and the second region, wherein:
the further region includes a first dielectric material, a second dielectric material, and a third dielectric material,
the first dielectric material has a portion between the second dielectric material and the first region,

the second dielectric material has a portion between the third dielectric material and the first dielectric material,
the first dielectric material has a U-shaped cross-section, and
the third dielectric material has a U-shaped cross-section.

16. The IC device of claim 15 , wherein the second dielectric material does not have a U-shaped cross-section.

17. The IC device of claim 15 , wherein the portion of the first dielectric material is in contact with a portion of the second dielectric material.

18. The IC device of claim 17 , wherein a further portion of the first dielectric material is in contact with a portion of the third dielectric material.

19. The IC device of claim 15 , wherein a further portion of the first dielectric material is in contact with a portion of the third dielectric material.

20. The IC device of claim 1 , wherein the insulating material has a side surface aligned with the first side surface of the region.

Assignees

• Intel Corp

Inventors

• Ma Sean T
• Wei Andy Chih-Hung
• Bouche Guillaume

Classifications

• H10W72/015

  of bond wires · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D62/235

  of IGFETs (IGFETs having buried channels H10D30/637) · CPC title

• H10D62/151

  of IGFETs  (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713) · CPC title