Single wire serial interface and protocol for intra-chip communications
US-2026095205-A1 · Apr 2, 2026 · US
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Singh Rupesh patents
Singh Rupesh is listed as an inventor on 39 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Singh Rupesh |
| Total patents | 39 |
| First publication | Aug 14, 2018 |
| Latest publication | Apr 2, 2026 |
Notable patents
Publications ranked by popularity score, then publication date.
Fast, low area self-test for read-only memory
US-2026004864-A1 · Jan 1, 2026 · US
Control of skew between multiple data lanes
US-12463650-B2 · Nov 4, 2025 · US
Low overhead loop back test for high speed transmitter
US-12449478-B2 · Oct 21, 2025 · US
Method and architecture for serial link characterization by arbitrary size pattern generator
US-12436853-B2 · Oct 7, 2025 · US
Low latency reset synchronizer circuit
US-2024364347-A1 · Oct 31, 2024 · US
High throughput digital filter architecture for processing unary coded data
US-12093193-B2 · Sep 17, 2024 · US
High throughput parallel architecture for recursive sinusoid synthesizer
US-12086568-B2 · Sep 10, 2024 · US
Data bridge for interfacing source synchronous datapaths with unknown clock phases
US-11989148-B2 · May 21, 2024 · US
Control of skew between multiple data lanes
US-2024039545-A1 · Feb 1, 2024 · US
Recent patents
Latest publications not already listed above.
Low overhead loop back test for high speed transmitter
US-2023266387-A1 · Aug 24, 2023 · US
High throughput parallel architecture for recursive sinusoid synthesizer
US-2023251829-A1 · Aug 10, 2023 · US
High throughput parallel architecture for recursive sinusoid synthesizer
US-11656848-B2 · May 23, 2023 · US
Low power finite impulse response filter
US-2023033569-A1 · Feb 2, 2023 · US
High speed data weighted averaging (DWA) to binary converter circuit
US-11563443-B2 · Jan 24, 2023 · US
Method and device for testing successive approximation register analog-to-digital converters
US-11463098-B2 · Oct 4, 2022 · US
First order memory-less dynamic element matching technique
US-11417371-B2 · Aug 16, 2022 · US
Clock and data recovery circuit
US-11411565-B2 · Aug 9, 2022 · US
Data bridge for interfacing source synchronous datapaths with unknown clock phases
US-2022206987-A1 · Jun 30, 2022 · US
Method and architecture for serial link characterization by arbitrary size pattern generator
US-2022188203-A1 · Jun 16, 2022 · US
High speed data weighted averaging (dwa) to binary converter circuit
US-2022069837-A1 · Mar 3, 2022 · US
Method and device for testing successive approximation register analog-to-digital converters
US-2022006467-A1 · Jan 6, 2022 · US
First order memory-less dynamic element matching technique
US-2021343319-A1 · Nov 4, 2021 · US
First order memory-less dynamic element matching technique
US-11094354-B2 · Aug 17, 2021 · US
Digital sinusoid generator
US-11092993-B2 · Aug 17, 2021 · US
Clock and data recovery circuit
US-2021211133-A1 · Jul 8, 2021 · US
Sigma-delta analog-to-digital converter circuit with correction for mismatch error introduced by the feedback digital-to-analog converter
US-11043960-B2 · Jun 22, 2021 · US
High throughput digital filter architecture for processing unary coded data
US-2021133124-A1 · May 6, 2021 · US
First order memory-less dynamic element matching technique
US-2021110852-A1 · Apr 15, 2021 · US
High throughput parallel architecture for recursive sinusoid synthesizer
US-2021081174-A1 · Mar 18, 2021 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| St Microelectronics Int Nv | 29 |
| St Microelectronics Int Nv | 9 |
| St Microelectronics Int Nv | 1 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| H03K3/037 | 10 |
| H03M3/464 | 8 |
| G06F1/022 | 6 |
| H03B28/00 | 6 |
| G06F7/5443 | 6 |