Clock and data recovery circuit

Patent metadata

Field	Value
Publication number	US-11411565-B2
Application number	US-202017131917-A
Country	US
Kind code	B2
Filing date	Dec 23, 2020
Priority date	Jan 6, 2020
Publication date	Aug 9, 2022
Grant date	Aug 9, 2022

Abstract

A first sampling circuit takes phase offset first samples of a received serial data stream in response to a first edge of a sampling clock and a first comparator circuit determines whether the plurality of phase offset first samples have a same logic state. A second sampling circuit takes phase offset second samples of the received serial data stream in response to a second edge of the sampling clock, opposite the first edge, and a second comparator circuit determines whether the phase offset second samples have a same logic state. One of the first samples or one of the second samples is then selected in response to the determinations made by the first and second comparator circuits. A serial to parallel converter circuit generates an output word including the selected one of the first and second samples.

First claim

What is claimed is:

1. A circuit, comprising:
a first sampling circuit configured to take a plurality of phase offset first samples of a received serial data stream in response to a first edge of a sampling clock;
a second sampling circuit configured to take a plurality of phase offset second samples of the received serial data stream in response to a second edge of the sampling clock, wherein the second edge is opposite the first edge;
a first comparator circuit configured to determine whether the plurality of phase offset first samples have a same logic state;
a second comparator circuit configured to determine whether the plurality of phase offset second samples have a same logic state;
a first selection circuit configured to select one of the first samples or one of the second samples in response to the determinations made by the first and second comparator circuits; and
a serial to parallel converter circuit configured to generate an output word including the selected one of the first and second samples.

2. The circuit of claim 1 , wherein the first selection circuit comprises:
a first multiplexer having a first input configured to receive said one of the first samples and a second input configured to receive said one of the second samples; and
a first control circuit configured to generate a first selection signal for controlling the first multiplexer in response to the determinations made by the first and second comparator circuits.

3. The circuit of claim 2 , wherein the first control circuit comprises a set-reset latch circuit that is set in response to the determination made by the first comparator circuit to generate the first selection signal in a first logic state and reset in response to the determination made by the second comparator circuit to generate the first selection signal in a second logic state.

4. The circuit of claim 3 , wherein the first selection signal in the first logic state causes the first multiplexer to select said one of the second samples for use by the serial to parallel converter circuit, and wherein the first selection signal in the second logic state causes the first multiplexer to select said one of the first samples for use by the serial to parallel converter circuit.

5. The circuit of claim 1 , further comprising a second selection circuit configured to select the first selection circuit selected one of the first samples or one of the second samples or a logical inverse of a previously selected one of the first or second samples in response to the determinations made by the first and second comparator circuits.

6. The circuit of claim 5 , wherein the second selection circuit comprises:
a second multiplexer having a first input configured to receive said first selection circuit selected one of the first samples or one of the second samples and a second input configured to receive said logical inverse of the previously selected one of the first or second samples; and
a second control circuit configured to generate a second selection signal for controlling the second multiplexer in response to the determinations made by the first and second comparator circuits.

7. The circuit of claim 6 , wherein the second control circuit:
generates the second control signal in a first logic state to cause the second multiplexer to select said logical inverse of the previously selected one of the first or second samples for use by the serial to parallel converter circuit in response to the first comparator circuit determining that the plurality of phase offset first samples do not have the same logic state and the second comparator circuits determining that the plurality of phase offset second samples do not have the same logic state; and
otherwise generates the second control signal in a second logic state to cause the second multiplexer to select said first selection circuit selected one of the first samples or one of the second samples for use by the serial to parallel converter circuit.

8. The circuit of claim 6 , wherein the second control circuit:
generates the second control signal in a first logic state to cause the second multiplexer to select said logical inverse of the previously selected one of the first or second samples for use by the serial to parallel converter circuit in response to the first comparator circuit determining that the plurality of phase offset first samples have the same logic state and the second comparator circuit determining that the plurality of phase offset second samples have the same logic state and where the logic states of the plurality of phase offset first samples and plurality of phase offset second samples are different; and
otherwise generates the second control signal in a second logic state to cause the second multiplexer to select said first selection circuit selected one of the first samples or one of the second samples for use by the serial to parallel converter circuit.

9. The circuit of claim 1 , further comprising a jitter detection circuit configured to detect a jitter condition relative to the sampling clock and select a number of clock cycles of the sampling clock for each output word generated by the serial to parallel converter circuit.

10. The circuit of claim 9 , wherein the jitter detection circuit monitors the determinations made by the first and second comparator circuits to detect instances of detected logic transition of the received serial data stream over time in order to detect a jitter condition and in response thereto controls the serial to parallel converter circuit to generate an N-bit output word from N selected ones of the first and second samples over a time period having N+1 cycles of the sampling clock.

11. The circuit of claim 9 , wherein the jitter detection circuit monitors the determinations made by the first and second comparator circuits to detect instances of detected logic transition of the received serial data stream over time in order to detect a jitter condition and in response thereto controls the serial to parallel converter circuit to generate an N-bit output word from at least selected ones of the first and second samples over a time period having N−1 cycles of the sampling clock.

12. The circuit of claim 11 , further comprising a shift register storing a plurality of second samples of the received serial data stream, and wherein the N-bit output word generated by the serial to parallel converter circuit includes less than N selected ones of the first and second samples and one or more of the second samples from the shift register.

13. The circuit of claim 9 , wherein the jitter detection circuit monitors the determinations made by the first and second comparator circuits to detect instances of detected logic transition of the received serial data stream over time in order to detect a no jitter condition and in response thereto controls the serial to parallel converter circuit to generate an N-bit output word from N selected ones of the first and second samples over a time period having N cycles of the sampling clock.

14. The circuit of claim 1 , wherein the output word is generated by the serial to parallel converter circuit over a plurality of cycles of the sampling clock and further comprising a control circuit configured to output a recovered clock signal having a period equal to said plurality of cycles of the sampling clock.

15. A method, comprising:
sampling a received serial data stream in response to a first edge of a sampling clock to obtain a plurality of phase offset first samples;
sampling the received serial data stream in response to a second edge of the sampling clock, wherein the s

Assignees

• St Microelectronics Int Nv

Inventors

• Singh Rupesh
• Bal Ankur

Classifications

• H03L7/085 Primary

  concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal (H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00) · CPC title

• G06F1/04

  Generating or distributing clock signals or signals derived directly therefrom · CPC title

• H03L7/0807 Primary

  concerning mainly a recovery circuit for the reference signal · CPC title

• H04L7/0338 Primary

  the correction of the phase error being performed by a feed forward loop · CPC title

• H03L7/091

  the phase or frequency detector using a sampling device (H03L7/087 takes precedence) · CPC title