High throughput digital filter architecture for processing unary coded data

Patent metadata

Field	Value
Publication number	US-12093193-B2
Application number	US-202017067967-A
Country	US
Kind code	B2
Filing date	Oct 12, 2020
Priority date	Nov 6, 2019
Publication date	Sep 17, 2024
Grant date	Sep 17, 2024

Abstract

Individual bits of a K bit unary data word, wherein K is greater than one, are applied to K polyphase finite impulse response filter circuits. Each polyphase finite impulse response filter circuit receives a different bit and operates with a single bit precision to generate from each received bit a filtered output data word. A gain adjustment is applied by a gain stage circuit to each filtered output data word to generate a corresponding gain adjusted output data word. The gain adjusted output data words from the gain stage circuits are summed to generate an output data word. The unary data word may be output from a source such as a data encoder or a quantizer.

First claim

What is claimed is:

1. A circuit, comprising:
an input configured to receive a K bit unary coded data word, wherein K is greater than one;
K polyphase finite impulse response filter circuits, each polyphase finite impulse response filter circuit receiving a different single bit of the K bit unary coded data word and generating therefrom a filtered output data word, each polyphase finite impulse response filter circuit having a single bit precision;
K gain stage circuits, each gain stage circuit applying a gain adjustment to the filtered output data word from a corresponding polyphase finite impulse response filter circuit to generate a gain adjusted output data word; and
a summation circuit summing the gain adjusted output data words from the K gain stage circuits to generate each output data word.

2. The circuit of claim 1 , wherein the input receives a stream of the K bit unary coded data words at a rate Fs, and each polyphase finite impulse response filter circuit generates a stream of the filtered output data words at a rate Fs/N, wherein N is greater than one.

3. The circuit of claim 2 , wherein N is a number of partial polyphase filter computation circuits within each polyphase finite impulse response filter circuit.

4. The circuit of claim 3 , wherein each partial polyphase filter computation circuit is a multiply and accumulate circuit (MAC).

5. The circuit of claim 4 , wherein each MAC includes a delay circuit, and wherein the delay circuit is a single bit delay element.

6. The circuit of claim 5 , wherein the single bit delay element is a flip-flop.

7. The circuit of claim 2 , wherein N is a number of phases for an implementation of the polyphase finite impulse response filter circuit.

8. The circuit of claim 1 , wherein the gain adjustment for each gain stage circuit provides for a fractional correction of the unary coded data word.

9. The circuit of claim 1 , further comprising a source circuit configured to supply the K bit unary coded data word.

10. The circuit of claim 9 , wherein the source circuit is a quantizer.

11. The circuit of claim 10 , wherein the quantizer is part of a Delta-Sigma analog-to-digital converter.

12. The circuit of claim 9 , wherein the source circuit is a data encoder.

13. A method, comprising:
receiving a K bit unary coded data word, wherein K is greater than one;
for each bit of the K bit unary coded data word, performing a polyphase finite impulse response filtering to generate from each bit a filtered output data word, wherein performing polyphase finite impulse response filtering comprises performing the filtering with a single bit precision;
applying a gain adjustment to each filtered output data word from a corresponding polyphase finite impulse response filtering to generate a gain adjusted output data word; and
summing the gain adjusted output data words to generate each output data word.

14. The method of claim 13 , wherein receiving comprises receiving a stream of the K bit unary coded data words at a rate Fs, and wherein the polyphase finite impulse response filtering generates a stream of the filtered output data words at a rate Fs/N, wherein N is greater than one.

15. The method of claim 14 , wherein N is a number of partial filter computations performed for each polyphase finite impulse response filtering.

16. The method of claim 14 , wherein each partial filter computation comprises performing a multiply and accumulate operation.

17. The method of claim 14 , wherein N is a number of phases for an implementation of the polyphase finite impulse response filtering.

18. The method of claim 13 , wherein applying the gain adjustment comprises implementing a fractional correction of the unary data word.

19. The method of claim 13 , further comprising supplying the K bit unary coded data word from source circuit.

20. The method of claim 19 , wherein the source circuit is a quantizer.

21. The method of claim 20 , wherein the quantizer is part of a Delta-Sigma analog-to-digital converter.

22. The method of claim 19 , wherein the source circuit is a data encoder.

Assignees

• St Microelectronics Int Nv

Inventors

• Bal Ankur
• Singh Rupesh

Classifications

• G06F9/3001

  Arithmetic instructions · CPC title

• G06F9/30021

  Compare instructions, e.g. Greater-Than, Equal-To, MINMAX · CPC title

• G06F17/16

  Matrix or vector computation {, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization (matrix transposition G06F7/78)} · CPC title

• G06F7/4876

  Multiplying · CPC title

• G06F7/5443

  Sum of products (for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00) · CPC title