Data bridge for interfacing source synchronous datapaths with unknown clock phases

Patent metadata

Field	Value
Publication number	US-11989148-B2
Application number	US-202117548101-A
Country	US
Kind code	B2
Filing date	Dec 10, 2021
Priority date	Dec 30, 2020
Publication date	May 21, 2024
Grant date	May 21, 2024

Abstract

An integrated circuit includes a first subsystem including a first clock generator configured to generate a first clock signal. The integrated circuit also includes a second subsystem including a second clock generator configured to generate a second clock signal. The first subsystem include a clock edge selector configured to determine a phase difference between the first clock signal and the second clock signal and to select, based on the phase difference, either a rising edge or a falling edge of the second clock signal to control output of data from the first subsystem to the second subsystem.

First claim

The invention claimed is:

1. A method, comprising:
generating a first clock signal with a first subsystem of an integrated circuit;
generating a second clock signal with a second subsystem of the integrated circuit;
determining a phase difference between the first clock signal and the second clock signal; and
selecting an edge of the second clock signal based on the phase difference;
controlling transmission of data from the first subsystem to the second subsystem with the selected edge of the second clock signal;
generating, with the first subsystem, a first phase signal having a same frequency as the first clock signal and a first selected phase difference relative to the first clock signal; and
generating, with the first subsystem, a second phase signal having the same frequency as the first clock signal and a second selected phase difference relative to the first clock signal.

2. The method of claim 1 , further comprising determining the phase difference by identifying whether a rising edge of the second clock signal occurs between a rising edge of the first phase signal and a rising edge of the second phase signal.

3. The method of claim 2 , further comprising determining the phase difference by identifying whether the rising edge of the second clock signal and a rising edge of the first clock signal occur between the rising edge of the first phase signal and the rising edge of the second phase signal.

4. The method of claim 3 , further comprising controlling transmission with the rising edge of the second clock signal if the rising edge of the second clock signal does not occur between the rising edge of the first phase signal and the rising edge of the second phase signal.

5. The method of claim 4 , wherein controlling transmission of data with the rising edge of the second clock signal includes providing the second clock signal to clock input terminals of flip-flops of the first subsystem.

6. The method of claim 4 , further comprising controlling transmission with a falling edge of the second clock signal if the rising edge of the second clock signal occurs between the rising edge of the first phase signal and the rising edge of the second phase signal.

7. The method of claim 6 , wherein controlling transmission of data with the rising edge of the second clock signal includes providing a complimentary second clock signal to clock input terminals of flip-flops of the first subsystem, wherein the complimentary second clock signal is a logical compliment of the second clock signal.

8. The method of claim 7 , wherein generating the complimentary second clock signal includes providing the second clock signal to an inverter.

9. The method of claim 7 , further comprising providing the second clock signal and the complimentary second clock signal to a multiplexer.

10. The method of claim 9 , wherein selectively controlling transmission of data includes outputting either the second clock signal or the complimentary second clock signal from the multiplexer.

11. An integrated circuit, comprising:
a first subsystem including:
a first clock generator configured to generate first clock signal;
a clock edge selector coupled to the first clock generator;
a phase generator configured to generate, from the first clock signal, a first phase signal having a first selected phase difference with the first clock signal and a second phase signal having a second selected phase difference with the first clock signal; and

a second subsystem including:
a second clock generator configured to generate a second clock signal, the clock edge selector is configured to determine a phase difference between the first clock signal and the second clock signal and to select, based on the phase difference, either a rising edge or a falling edge of the second clock signal to control output of data from the first subsystem to the second subsystem.

12. The integrated circuit of claim 11 , wherein the clock edge selector determines the phase difference by comparing the second clock signal to the first and second phase signals.

13. The integrated circuit of claim 11 , further comprising a plurality of flip-flops coupled to the clock edge selector, wherein the clock edge selector is configured to invert the second clock signal to generate a complimentary second clock signal, wherein the clock edge selector is configured to provide to the flip-flops either the second clock signal or the complimentary second clock signal based on the phase difference.

14. A method, comprising:
generating, with a first subsystem of an integrated circuit, a first clock signal;
generating, with a second subsystem of the integrated circuit, a second clock signal;
generating with the first subsystem, a complimentary second clock signal that is a logical compliment of the second clock signal;
detecting a phase difference between the second clock signal and the first clock signal;
selectively controlling data output circuitry of the first subsystem with either the second clock signal or the complimentary second clock signal based on the phase difference, wherein selectively controlling data output circuitry includes selectively providing either the second clock signal or the complimentary second clock signal to clock terminals of first flip-flops of the first subsystem based on the phase difference;
passing data from the first flip-flops to second flip-flops of the first subsystem; and
providing the second clock signal to clock terminals of the second flip-flops.

15. The method of claim 14 , further comprising passing the data from the second flip-flops to the second subsystem.

16. The method of claim 15 , further comprising:
receiving the data with data input circuitry of the second subsystem; and
controlling the data input circuitry with the second clock signal.

Assignees

• St Microelectronics Int Nv

Inventors

• Bal Ankur
• Singh Rupesh

Classifications

• G06F13/42 Primary

  Bus transfer protocol, e.g. handshake; Synchronisation · CPC title

• G06F1/06

  Clock generators producing several clock signals {(G06F1/08 - G06F1/14 take precedence)} · CPC title

• G06F1/08

  Clock generators with changeable or programmable clock frequency · CPC title

• H03K3/037

  Bistable circuits · CPC title

• G06F13/4068

  Electrical coupling · CPC title