Sigma-delta analog-to-digital converter circuit with correction for mismatch error introduced by the feedback digital-to-analog converter

Patent metadata

Field	Value
Publication number	US-11043960-B2
Application number	US-202016895183-A
Country	US
Kind code	B2
Filing date	Jun 8, 2020
Priority date	Jun 10, 2019
Publication date	Jun 22, 2021
Grant date	Jun 22, 2021

Abstract

A sigma-delta modulator includes an N-bit quantization circuit that generates a stream of N-bit code words and a feedback signal path with an N-bit DAC circuit, having a non-ideal operation due to mismatch error, that converts the stream of N-bit code words to generate a feedback signal. A digital DAC copy circuit provides a digital replication of the N-bit DAC circuit. The digital replication accounts for the non-ideal operation of the N-bit DAC circuit 126 due to mismatch error, and converts the stream of N-bit code words to generate a stream of P-bit code words, where P>N, that are functionally equivalent to the feedback signal output from the N-bit DAC circuit.

First claim

What is claimed is:

1. A sigma-delta modulator circuit, comprising:
a differencing circuit having a first input configured to receive an input signal and a second input configured to receive a feedback signal and an output configured to generate a difference signal;
a K-th order loop filter circuit configured to filter the difference signal and generate a change signal;
an N-bit quantization circuit configured to sample the change signal at a sampling frequency rate, quantize the sampled change signal and generate a stream of N-bit code words;
an N-bit digital-to-analog converter (DAC) circuit configured to convert the stream of N-bit code words to generate the feedback signal, wherein the N-bit DAC circuit has a non-ideal operation due to mismatch error that introduces an analog DAC error in the feedback signal; and
a digital DAC copy circuit that provides a digital replication of the N-bit DAC circuit, said digital replication accounting for the non-ideal operation of the N-bit DAC circuit due to mismatch error, the digital DAC copy circuit configured to convert the stream of N-bit code words to output a stream of P-bit code words, where P>N, that provide a digital value equivalent to an analog value of the feedback signal plus the analog DAC error that is output from the N-bit DAC circuit.

2. The circuit of claim 1 , wherein noise associated with the mismatch error is high pass noise shaped, further including a low pass filter configured to filter out high frequency components of the high pass noise shaped mismatch error.

3. The circuit of claim 2 , where the low pass filter is implemented by a decimation circuit configured to decimate the stream of P-bit code words at a decimation frequency rate to generate a stream of M-bit words, where M>P.

4. The circuit of claim 1 , further comprising a decimation circuit configured to decimate the stream of P-bit code words at a decimation frequency rate to generate a stream of M-bit words, where M>P.

5. The circuit of claim 1 , further comprising a calibration circuit configured to program the digital DAC copy circuit to provide the digital replication of the N-bit DAC circuit.

6. The circuit of claim 1 , wherein the digital DAC copy circuit includes a look-up table configured to translate N-bit code word generated by the N-bit quantization circuit to a corresponding P-bit code word for output by the digital DAC copy circuit.

7. A sigma-delta modulator circuit, comprising:
a differencing circuit having a first input configured to receive an input signal and a second input configured to receive a feedback signal and an output configured to generate a difference signal;
a K-th order loop filter circuit configured to filter the difference signal and generate a change signal;
an N-bit quantization circuit configured to sample the change signal at a sampling frequency rate, quantize the sampled change signal and generate a stream of N-bit code words;
an N-bit digital-to-analog converter (DAC) circuit configured to convert the stream of N-bit code words to generate the feedback signal, wherein the N-bit DAC circuit has a non-ideal operation due to mismatch error; and
a digital DAC copy circuit that provides a digital replication of the N-bit DAC circuit, said digital replication accounting for the non-ideal operation of the N-bit DAC circuit due to mismatch error, the digital DAC copy circuit configured to convert the stream of N-bit code words to output a stream of P-bit code words, where P>N, that are functionally equivalent to the feedback signal output from the N-bit DAC circuit; and
a calibration circuit configured to program the digital DAC copy circuit to provide the digital replication of the N-bit DAC circuit, wherein the calibration circuit comprises:
an estimation N-bit DAC circuit;
a further differencing circuit configured to generate the feedback signal as a difference between a first signal output from the N-bit DAC circuit and a second signal output from the estimation N-bit DAC circuit;
a first multiplexing circuit having a first input configured to receive the stream of N-bit code words and a second input configured to receive an N-bit calibration code word,
wherein an output of the first multiplexing circuit is applied to an input of the N-bit DAC circuit;

a second multiplexing circuit having a first input configured to receive an N-bit null code word and a second input configured to receive the stream of N-bit code words, wherein an output of the second multiplexing circuit is applied to an input of the estimation N-bit DAC circuit; and
a control and processing circuit having a first input configured to receive the stream of N-bit code words and an output configured to generate a programming signal for programming the digital DAC copy circuit, wherein the control and processing circuit controls the first and second multiplexing circuits in a calibration mode to select the second inputs, apply a value for the N-bit calibration code word, and process the stream of N-bit code words in response to the applied value to determine the mismatch error of the N-bit DAC circuit for the applied value in order to program the digital DAC copy circuit to provide the digital replication.

8. The circuit of claim 7 , wherein the control and processing circuit further applies a series of values for the N-bit calibration code word, and processes the stream of N-bit code words in response to the applied series of values to determine the mismatch error of the N-bit DAC circuit for the applied series of values in order to program the digital DAC copy circuit to provide the digital replication.

9. The circuit of claim 8 , wherein the applied series of values include all possible values for input to the N-bit DAC circuit.

10. The circuit of claim 7 , wherein the control and processing circuit further controls the first and second multiplexing circuits in a normal operating mode to select the first inputs.

11. A sigma-delta modulator circuit, comprising:
a differencing circuit having a first input configured to receive an input signal and a second input configured to receive a feedback signal and an output configured to generate a difference signal;
a K-th order loop filter circuit configured to filter the difference signal and generate a change signal;
an N-bit quantization circuit configured to sample the change signal at a sampling frequency rate, quantize the sampled change signal and generate a stream of N-bit code words;
an N-bit digital-to-analog converter (DAC) circuit configured to convert the stream of N-bit code words to generate the feedback signal, wherein the N-bit DAC circuit has a non-ideal operation due to mismatch error that introduces an analog DAC error in the feedback signal; and
a digital DAC copy circuit that provides a digital replication of the N-bit DAC circuit, said digital replication accounting for the non-ideal operation of the N-bit DAC circuit due to mismatch error, the digital DAC copy circuit configured to convert the stream of N-bit code words to output a stream of P-bit code words, where P>N, each P-bit code word comprising an addition of:
a first digital code corresponding to an ideal output of the N-bit DAC circuit in response to the N-bit code word; plus
a second digital code corresponding to the analog DAC error of the N-bit DAC circuit in response to the N-bit code word.

12. The circuit of claim 11 , wherein noise associated with the mismatch error is high pass noise shaped, further including a low pass filter configured to filter out high frequency components of the high pass noise shaped mismatch error.

13. The circuit of claim 12 , where the low pass filter is im

Assignees

• St Microelectronics Int Nv

Inventors

• Bal Ankur
• Singh Rupesh

Classifications

• H03M3/388 Primary

  by storing corrected or correction values in one or more digital look-up tables · CPC title

• H03M3/436

  characterised by the order of the loop filter, e.g. error feedback type · CPC title

• H03M3/458

  Analogue/digital converters using delta-sigma modulation as an intermediate step · CPC title

• H03M1/1019

  by storing a corrected or correction value in a digital look-up table · CPC title

• H03M1/1009 Primary

  Calibration · CPC title