Method and architecture for serial link characterization by arbitrary size pattern generator

Patent metadata

Field	Value
Publication number	US-12436853-B2
Application number	US-202217682167-A
Country	US
Kind code	B2
Filing date	Feb 28, 2022
Priority date	Aug 31, 2020
Publication date	Oct 7, 2025
Grant date	Oct 7, 2025

Abstract

A serial-connection is tested by transmitting a PRBS generated using a kth-order monic-polynomial from transmission-circuitry to reception-circuitry, and determining operation is proper based upon the PRBS received. The PRBS is formed by generating x intermediate-words of the PRBS, x being a result of an integer-divide between a total number of bits in the PRBS and a bit-width of a serializer that transmits the PRBS, generating a leading-word of the PRBS as having first y-bits of the PRBS as its LSBs, y being based upon a modulo-divide between the total number of bits in the PRBS and x, and generating a trailing-word of the PRBS as having last z-bits of the PRBS as its MSBs, z being based upon a difference between a result of the modulo-divide and y. The PRBS is transmitted sequentially as the leading-word of the PRBS, the intermediate-words of the PRBS, and the trailing-word of the PRBS.

First claim

The invention claimed is:

1. A method of testing a serial data connection, the method comprising:
transmitting a pseudo-random binary sequence (PRBS) generated using a kth order monic polynomial from transmission side circuitry to reception side circuitry over a physical link; and
determining whether the PRBS received at the reception side circuitry is as expected and/or determining electrical parameters of the physical link based on the PRBS received at the reception side circuitry, and indicating an error if the PRBS received at the reception side circuitry is not as expected or if the determined electrical parameters of the physical link demonstrate an error condition;
wherein the PRBS is generated by:
generating x intermediate words of the PRBS, with x being a result of an integer divide between a total number of bits in the PRBS and a bit-width of a serializer that transmits the PRBS over the serial data connection;
generating a leading word of the PRBS, the leading word having first y bits of the PRBS as its least significant bits, with y being based upon a modulo divide between the total number of bits in the PRBS and x; and
generating a trailing word of the PRBS, the trailing word having last z bits of the PRBS as its most significant bits, with z being based upon a difference between a result of the modulo divide and y; and

wherein the PRBS is transmitted by performing steps of transmitting the leading word of the PRBS, transmitting the x intermediate words of the PRBS, and transmitting the trailing word of the PRBS.

2. The method of claim 1 , wherein the leading word of the PRBS is generated as having its most significant bits as being zeroes.

3. The method of claim 1 , wherein the trailing word of the PRBS is generated as having its least significant bits as being zeroes.

4. The method of claim 1 , wherein the x intermediate words of the PRBS are generated using a hardware PRBS predictor that predicts the x intermediate words based upon a seed and outputs each intermediate word in a parallel fashion.

5. The method of claim 4 , wherein transmitting the leading word of the PRBS comprises selecting the leading word for serialization and transmission; wherein transmitting the x intermediate words of the PRBS comprises selecting the x intermediate words of the PRBS for serialization and transmission; and wherein transmitting the trailing word of the PRBS comprises selecting the trailing word for serialization and transmission.

6. The method of claim 5 , wherein the leading word of the PRBS is generated by reading from a memory element separate from the hardware PRBS predictor; and wherein the trailing word of the PRBS is generated by reading from the memory element.

7. The method of claim 5 , wherein the kth order monic polynomial comprises a 23 rd order monic polynomial; and wherein the bit-width of the serializer is 16 bits.

8. The method of claim 1 , wherein the kth order monic polynomial comprises a 23 rd order monic polynomial; and wherein the bit-width of the serializer is 16 bits.

9. The method of claim 1 , wherein the kth order monic polynomial comprises a monic polynomial that is odd in order; and wherein the bit-width of the serializer is even.

10. Transmission-side circuitry for use in a serial communications system, the transmission-side circuitry comprising:
a pattern generator configured to generate a pseudo-random binary sequence (PRBS) according to a kth order monic polynomial, the PRBS being generated as a series of words of a given bit size;
a serializer having a number of inputs equal in number to the given bit size, coupled to serially receive the series of words of the PRBS from the pattern generator, and producing a PRBS output; and
a line driver configured to transmit the PRBS output in a serial fashion over a physical link;
wherein the pattern generator comprises:
a PRBS predictor configured to generate x intermediate words of the PRBS based upon a received k-bit seed and output the x intermediate words in a parallel fashion, with x being a result of an integer divide between a total number of bits in the PRBS and the given bit size;
a multiplexer having: a first input set coupled to the PRBS predictor to receive the x intermediate words in a parallel fashion, and a second input set coupled to receive either a leading word or a trailing word in a parallel fashion;
wherein the leading word has first y bits of the PRBS as its least significant bits, with y being based upon a modulo divide between the total number of bits in the PRBS and x;
wherein the trailing word of the PRBS has last z bits of the PRBS as its most significant bits, with z being based upon a difference between a result of the modulo divide and y; and
a control circuit configured to receive the x intermediate words of the PRBS and based thereupon, control the multiplexer to sequentially output the leading word of the PRBS, output the x intermediate words of the PRBS, and output the trailing word of the PRBS.

11. The transmission-side circuitry of claim 10 , further comprising a memory element configured to store the leading word of the PRBS and the trailing word of the PRBS.

12. The transmission-side circuitry of claim 10 , wherein the kth order monic polynomial comprises a monic polynomial that is odd in order; and wherein the serializer has an even number of inputs.

13. The transmission-side circuitry of claim 10 , wherein the kth order monic polynomial comprises a 23 rd order monic polynomial; and wherein given bit size is 16 bits.

14. The transmission-side circuitry of claim 13 , wherein the PRBS predictor comprises:
23 flip flops clocked by a same clock signal and providing outputs in parallel to the multiplexer; and
16 multiplexers having outputs respectively coupled to inputs of 16 of the 23 flip flops, having first inputs respectively receiving k-bits of the k-bit seed, and having second inputs respectively receiving outputs of 16 exclusive-OR gates; wherein each of the 16 exclusive-OR gates has inputs coupled to different ones of the outputs of the 23 flip flops.

15. The transmission-side circuitry of claim 10 , wherein the leading word of the PRBS has its most significant bits as being zeroes.

16. The transmission-side circuitry of claim 10 , wherein the trailing word of the PRBS has its least significant bits as being zeroes.

Assignees

• St Microelectronics Int Nv

Inventors

• Bal Ankur
• Singh Rupesh

Classifications

• H04B17/0085

  using test signal generators · CPC title

• H04L1/242

  by comparing a transmitted test signal with a locally generated replica · CPC title

• G06F13/4282 Primary

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• G06F7/582

  Pseudo-random number generators · CPC title

• G06F11/221 Primary

  to test buses, lines or interfaces, e.g. stuck-at or open line faults · CPC title