First order memory-less dynamic element matching technique

Patent metadata

Field	Value
Publication number	US-11094354-B2
Application number	US-202017015271-A
Country	US
Kind code	B2
Filing date	Sep 9, 2020
Priority date	Oct 10, 2019
Publication date	Aug 17, 2021
Grant date	Aug 17, 2021

Abstract

A quantizer generates a thermometer coded signal from an analog voltage signal. Data weighted averaging (DWA) of the thermometer coded signal is accomplished by controlling the operation of a crossbar switch controlled by a switch control signal to generate an output DWA signal. The output DWA signal is latched to generate a latched output DWA signal which is processed along with bits of the thermometer coded input signal in feedback loop to generate the switch control signal. The latching of the output DWA signal is performed in an input register of a digital-to-analog converter which operates to convert the latched output DWA signal to a feedback analog voltage from which the analog voltage signal is generated. The switch control signal specifies a bit location for a beginning logic transition of the output DWA signal cycle based on detection of an ending logic transition of the latched DWA signal.

First claim

The invention claimed is:

1. A circuit, comprising:
a crossbar switch matrix having an input configured to receive a thermometer code signal and an output configured to output a data weighted averaging signal, wherein switching between the input and output by the crossbar switch matrix is controlled by a crossbar selection signal;
a data register configured to latch the output data weighted averaging signal and generate a latched data weighted averaging signal; and
a control circuit configured to receive the latched data weighted averaging signal and determine from bits of the latched data weighted averaging signal a bit location within the latched data weighted averaging signal where an ending logic transition occurs and generate the crossbar selection signal to control switching between the input and output by the crossbar switch matrix to select a bit location within the output data weighted averaging signal where a beginning logic transition occurs.

2. The circuit of claim 1 , wherein the latched data weighted averaging signal comprises a plurality of bits and wherein the control circuit comprises a combinational logic circuit configured to logically combine the plurality of bits of the latched data weighted averaging signal to detect the bit location of the latched data weighted averaging signal where the ending logic transition occurs.

3. The circuit of claim 2 , wherein the combinational logic circuit comprises a plurality of AND gates, each AND gate having a first input coupled to receive one bit of the latched data weighted averaging signal and a second input coupled to receive another bit of the latched data weighted averaging signal, wherein said one bit and said another bit are adjacent bits within the latched data weighted averaging signal.

4. The circuit of claim 3 , wherein the plurality of AND gates generate a selection input signal specifying the bit location of the latched data weighted averaging signal where the beginning logic transition occurs.

5. The circuit of claim 4 , wherein the selection input signal generated by the plurality of AND gates is directly applied to selection inputs of the crossbar switch matrix.

6. The circuit of claim 2 , further comprising a quantization circuit configured to generate the thermometer code signal at one of a leading or trailing edge of a clock signal and wherein the data register latches the output data weighted averaging signal at the other of the leading or trailing edge of the clock signal.

7. The circuit of claim 6 , further comprising a docked logic circuit comprising:
a detection circuit configured to detect an all logic 1 state or all logic 0 state for bits of the thermometer code signal; and
a logic circuit configured to force a certain logic state for one bit of the selection input signal in response to detection by the detection circuit of the all logic 1 state or all logic 0 state for bits of the thermometer code signal, the forced logic state being different from a logic state for said one bit of the selection input signal generated by the combinational logic circuit.

8. The circuit of claim 7 , wherein the logic circuit includes a flip-flop configured to store a value of a signal output by the detection circuit in response to said other of the leading or trailing edge of the clock signal.

9. The circuit of claim 8 , wherein the logic circuit further includes a logic OR gate configured to logically combine an output of the flip-flop and said one bit of the selection input signal generated by the combinational logic circuit.

10. The circuit of claim 1 , wherein the thermometer code signal includes a plurality of bits and wherein the output data weighted averaging signal includes a plurality of bits, said crossbar switch matrix operating to selectively connect the bits of the thermometer code signal to the bits of the output data weighted averaging signal in a sequence having a barrel shifted position specified by the crossbar selection signal.

11. The circuit of claim 10 , wherein the barrel shifted position places the bit location for the beginning logic transition for the output data weighted averaging signal adjacent to the bit location for the ending logic transition for the latched data weighted averaging signal.

12. The circuit of claim 1 , further comprising:
a digital-to-analog converter circuit having in an input register formed by said data register, said digital-to-analog, converter circuit configured to convert the latched data weighted averaging signal to a first analog voltage.

13. The circuit of claim 12 , further comprising:
a summation circuit configured to receive the first analog voltage and a second analog voltage and generate a difference analog voltage from the first and second analog voltages;
a loop filter configured to filter the difference analog voltage to generate a filtered analog voltage; and
a quantization circuit configured to quantize the filtered analog voltage to generate the thermometer code signal.

14. The circuit of claim 13 , wherein the quantization circuit generates the thermometer code signal at one of a leading or trailing edge of a clock signal and wherein the data register latches the output data weighted averaging signal at the other of the leading or trailing edge of the clock signal.

15. A circuit, comprising:
an input data bus carrying a multi-bit input data word in thermometer coded format;
a crossbar switch matrix having switch inputs coupled to the input data bus to receive the multi-bit input data word and switch outputs configured to output a multi-bit output data word that is a data weighted averaging (DWA) conversion of the thermometer coded multi-bit input data word;
a data register configured to latch the multi-bit output data word and generate a latched multi-bit output data word; and
a DWA control circuit configured to receive the latched multi-bit output data word and generate from the latched multi-bit output data word a multi-bit selection signal that is applied by a selection data bus to control inputs of the crossbar switch matrix;
wherein the crossbar switch matrix is configured to operate in response to the multi-bit selection signal to selectively map the switch inputs to the switch outputs to effectuate the DWA conversion of the thermometer coded multi-bit input data word to output the multi-bit output data word.

16. The circuit of claim 15 , wherein the DWA control circuit is configured to receive bits of the thermometer coded multi-bit input data word, and force a certain mapping of switch inputs to the switch outputs if the received bits of the thermometer coded multi-bit input data word indicate that all hits of the thermometer coded multi-bit input data word are either logic 1 or logic 0.

17. The circuit of claim 16 , wherein the DWA control circuit comprises a clocked logic circuit including:
an exclusive NOR gate configured to receive said bits of the thermometer coded multi-bit input data word;
a flip-flop configured to store an output from the exclusive NOR gate in response to a clock signal which also controls latching by the data register; and
an OR gate responsive to an output of the flip-flop and configured to generate a bit of the multi-bit selection signal.

18. The circuit of claim 15 , wherein the DWA control circuit is configured to generate the multi-bit selection signal in a manner such that only one bit in the multi-bit selection signal is asserted at a time.

19. The circuit of claim 18 , wherein said crossbar switch matrix operates to selectively connect bits of the th

Assignees

• St Microelectronics Int Nv

Inventors

• Bal Ankur
• Singh Rupesh
• Tripathi Vivek

Classifications

• G11C7/1087

  Data input latches · CPC title

• H03L7/1075

  by changing characteristics of the loop filter, e.g. changing the gain, changing the bandwidth (H03L7/1072 takes precedence) · CPC title

• G11C7/222

  Clock generating, synchronizing or distributing circuits within memory device · CPC title

• G11C7/04

  with means for avoiding disturbances due to temperature effects · CPC title

• G11C7/1012 Primary

  Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating · CPC title