Low overhead loop back test for high speed transmitter

Patent metadata

Field	Value
Publication number	US-12449478-B2
Application number	US-202318168496-A
Country	US
Kind code	B2
Filing date	Feb 13, 2023
Priority date	Feb 23, 2022
Publication date	Oct 21, 2025
Grant date	Oct 21, 2025

Abstract

An integrated circuit includes a serializer configured to receive first test data in n-bit words and to generate a single bit data stream by serializing the test data in accordance with a first clock signal. The integrated circuit includes testing circuitry configured to test the serializer without utilizing a deserializer.

First claim

The invention claimed is:

1. A method, comprising:
dividing a first clock signal having a first frequency to obtain a second clock signal having a second frequency lower than the first frequency;
providing first test data in a series of words to a serializer in accordance with the second clock signal;
generating, at the serializer, a single bit data stream by serializing the test data in accordance with the first clock signal;
generating a plurality of phase signals offset from each other in phase and each having the second frequency; and
generating second test data by sampling the single bit data stream in accordance with each of the plurality of phase signals.

2. The method of claim 1 , comprising determining an accuracy of the serializer based on the test data.

3. The method of claim 2 , wherein determining an accuracy of the serializer includes:
generating a signature from the second test data; and
comparing the signature to a reference signature based on the first test data.

4. The method of claim 3 , comprising:
passing the second test data to a serial input signature register; and
generating the signature with the serial input signature register.

5. The method of claim 2 , wherein generating the second test data includes:
receiving the single bit data stream a data input terminal of a flip-flop;
receiving, at a clock terminal of the flip flop, each of the plurality of phase signals sequentially.

6. The method of claim 5 , wherein each word includes n bits, wherein the plurality of phase signals includes n phase signals, where n is an integer number.

7. The method of claim 6 , wherein each of the n-phase signals is aligned to enable the flip-flop to capture, from the single-bit data stream, a respective bit-place of the words.

8. The method of claim 7 , wherein the first test data includes m words, where m is an integer number, wherein generating the second test data includes capturing, for each phase signal, m bits from the single bit data stream.

9. The method of claim 8 , comprising:
receiving the m words of the first test data at the serializer n times;
capturing m bits of the first test data from the single bit data stream with each phase signal; and
switching to a next phase signal at the clock terminal each time the m words of the first test data have been serialized by the serializer.

10. An integrated circuit, comprising:
a phase signal generator configured to receive a first clock signal having a first frequency, to generate a second clock signal having a second frequency lower than the first frequency by diving the first clock signal, and to generate a plurality of phase signals each having the second frequency;
a test data generator configured to output first test data in accordance with the second clock signal;
a serializer configured to generate a single bit data stream by serializing the first test data in accordance with the first clock signal, the serializer including:
an input coupled to the test data generator and configured to receive the test data; and
an output configured to output the single bit data stream;

a phase selector including:
a plurality of inputs each configured to receive a respective phase signal of the plurality of phase signals; and
an output configured to output a selected phase signal of the plurality of phase signals;

a flip-flop including:
a clock input terminal coupled to the output of the phase selector and configured to receive the selected phase signal;
a data input terminal coupled to an output of the serializer; and
a data output terminal.

11. The integrated circuit of claim 10 , comprising a single input signature generator including an input coupled to the data output terminal of the flip-flop.

12. The integrated circuit of claim 11 , wherein the test generator is configured to provide first test data in n-bit words to the input of the serializer, where n is an integer number.

13. The integrated circuit of claim 12 , wherein the phase signal generator is configured to generate, from the first clock signal, n phase signals each having a frequency of 1/nth a frequency of the first clock signal and out of phase with each other.

14. The integrated circuit of claim 12 , wherein the phase selector receives at its inputs the n phase signals and outputs one of the n phase signals to the clock terminal of the flip-flop based on a phase selection signal.

15. The integrated circuit of claim 14 , wherein the flip flop generates second test data from the single bit data stream by capturing with each of the n phase signals a respective portion of the first data.

16. The integrated circuit of claim 11 , wherein the single input signature generator is configured to generate a signature from the second test data.

17. The integrated circuit of claim 16 , comprising a comparison circuit configured to compare the signature to a reference signature based on the first test data.

18. An integrated circuit, comprising:
a phase signal generator configured to generate, from a first clock signal having a first frequency, a second clock signal and n phase signals each having a second frequency that is 1/nth a frequency of the first clock signal, the n phase signals being out of phase with each other, where n is an integer number;
a test data generator configured to output first test data in n-bit words in accordance with the second clock signal;
a serializer configured to receive the first test data from the test data generator and to serialize the test data in accordance with the first clock signal to generate a single bit data stream;
a phase selector configured to receive the n phase signals and to sequentially output the n phase signals one at a time based on a phase selection signal; and
a flip-flop configured to receive, on a clock terminal, the n phase signals from the phase selector, and to receive the single bit data stream on a data input terminal.

19. The integrated circuit of claim 18 , wherein the flip flop is configured to generate second test data by sampling the single bit data stream in accordance with each of the n phase signals.

20. The integrated circuit of claim 19 , comprising a single input signature register configured to receive the second test data and to generate a signature from the second test data.

Assignees

• St Microelectronics Int Nv

Inventors

• Singh Rupesh
• Bal Ankur

Classifications

• H03M9/00

  Parallel/series conversion or vice versa (digital stores in which the information is moved stepwise per se G11C19/00) · CPC title

• G01R31/2851

  Testing of integrated circuits [IC] (G01R31/317 takes precedence; testing individual devices G01R31/26; testing printed circuits G01R31/2801) · CPC title

• G01R31/31725

  Timing aspects, e.g. clock distribution, skew, propagation delay (for tester hardware G01R31/31937) · CPC title

• G01R31/00

  Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere ({measuring superconductive properties G01R33/1238;} testing line transmission systems H04B3/46; testing or measuring semiconductors or solid state devices during manufacture {H10P74/00}) · CPC title

• G01R31/31716 Primary

  Testing of input or output with loop-back · CPC title