High speed data weighted averaging (DWA) to binary converter circuit

Patent metadata

Field	Value
Publication number	US-11563443-B2
Application number	US-202117374351-A
Country	US
Kind code	B2
Filing date	Jul 13, 2021
Priority date	Aug 31, 2020
Publication date	Jan 24, 2023
Grant date	Jan 24, 2023

Abstract

A latch circuit sequentially latches a first data weighted averaging (DWA) data word and then a second DWA data word. A first detector circuit identifies a first bit location in the first DWA data that is associated with an ending of a first string of logic 1 bits in the first DWA data word. A second detector circuit identifies a second bit location in the second DWA data word associated with an ending of a second string of logic 1 bits in the second DWA data word. A DWA-to-binary conversion circuit converts the second DWA data word to a binary word by using the first bit location and second bit location to identify a number of logic 1 bits present in said second DWA data word. A binary value for that binary word that is equal to the identified number is output.

First claim

The invention claimed is:

1. A circuit for converting a data weighted averaging (DWA) data word into a binary word, comprising:
a first detector circuit configured to identify a first bit location in said DWA data word where a string of logic 1 bits begins;
a second detector circuit configured to identify a second bit location in said DWA data word where said string of logic 1 bits ends; and
a logic circuit comprising:
a plurality of first multiplexers, each first multiplexer having a selection input receiving said first bit location and each first multiplexer having inputs receiving a different order of binary values which represent possible numbers of logic 1 bits present in the DWA word; and
a second multiplexer having inputs coupled to outputs of the first multiplexers of said plurality of first multiplexers and having a selection input receiving said second bit location.

2. The circuit of claim 1 , further comprising:
a third detector circuit configured to identify whether all bits of said DWA data word are logic 0; and
a third multiplexer having a first input coupled to an output of the second multiplexer and a second input receiving a binary zero value and having a selection input receiving an all logic 0 identification output from the third detector circuit, the third multiplexer passing the second input in response to the all logic 0 identification.

3. The circuit of claim 1 , further comprising:
a third detector circuit configured to identify whether all bits of said DWA data word are logic 1; and
a third multiplexer having a first input coupled to an output of the second multiplexer and a second input receiving a maximum binary value and having a selection input receiving an all logic 1 identification output from the third detector circuit, the third multiplexer passing the second input in response to the all logic 1 identification.

4. The circuit of claim 1 , wherein the order of binary values which represent possible numbers of logic 1 bits present in the DWA word is barrel shifted across the first multiplexers of said plurality of first multiplexers.

5. A method, comprising:
receiving a data weighted averaging (DWA) data word;
identifying a first bit location in said DWA data word where a string of logic 1 bits begins;
identifying a second bit location in said DWA data word where said string of logic 1 bits ends;
selecting a sequence of binary values which represent possible numbers of logic 1 bits present in the DWA word starting from the identified first bit location;
choosing one binary value from said sequence using the identified a second bit location; and
outputting the chosen binary value as a binary word identifying a number of logic 1 bits which are present in said DWA data word.

6. The method of claim 5 , further comprising:
identifying whether all bits of said DWA data word are logic 0; and
if all bits are identified as logic 0, then outputting a binary zero value as the binary word.

7. The method of claim 5 , further comprising:
identifying whether all bits of said DWA data word are logic 1; and
if all bits are identified as logic 1, then outputting a binary maximum value as the binary word.

8. A method, comprising:
receiving a first data weighted averaging (DWA) data word;
processing said first DWA data word to identify a first bit location associated with an ending of a first string of logic 1 bits in said first DWA data word;
generating a second DWA data word including a second string of logic 1 bits that begins at said first bit location;
processing said second DWA data word to identify a second bit location associated with an ending of the second string of logic 1 bits in said second DWA data word;
using the first bit location and second bit location to identify a number of logic 1 bits present in said second DWA data word; and
outputting a binary value which is equal to said identified number.

9. The method of claim 8 , wherein using comprises:
generating from the first bit location a sequence of binary values which represent possible numbers of logic 1 bits present in the second DWA word starting from the first bit location; and
selecting one binary value from said sequence using the second bit location;
wherein outputting comprises outputting the selected binary value.

10. The method of claim 8 , further comprising:
identifying whether all bits of said second DWA data word are logic 0; and
wherein outputting comprises, if all bits are identified as logic 0, outputting a binary zero value.

11. The method of claim 8 , further comprising:
identifying whether all bits of said second DWA data word are logic 1; and
therein outputting comprises, if ail bits are identified as logic 1, outputting a binary maximum value.

12. A circuit, comprising:
a latch circuit configured to first latch a first data weighted averaging (DWA) data word and then second latch a second DWA data word;
a first detector circuit configured to identify a first bit location in said first DWA data word associated with an ending of a first string of logic 1 bits in said first DWA data word;
a second detector circuit configured to identify a second bit location in said second DWA data word associated with an ending of a second string of logic 1 bits in said second DWA data word; and
a DWA-to-binary conversion circuit configured to convert the second DWA data word to a binary word by using the first bit location and second bit location to identify a number of logic 1 bits present in said second DWA data word and outputting a binary value for said binary word which is equal to said identified number.

13. The circuit of claim 12 , further including a plurality of unary output elements selectively actuated by bits of the first and second DWA data words to generate corresponding first and second analog voltages.

14. The circuit of claim 13 , Therein the latch circuit and plurality of unary output elements are components of a digital-to-analog converter (DAC) circuit.

15. The circuit of claim 14 , further comprising:
a summation circuit configured to receive an input analog voltage and a feedback analog voltage derived from at least one of said first and second analog voltage and generate a difference analog voltage;
a loop filter configured to filter the difference analog voltage to generate a filtered analog voltage; and
a quantization circuit configured to quantize the filtered analog voltage to generate thermometer data words.

16. The circuit of claim 15 , further comprises a DWA circuit having an input receiving the thermometer data words and an output generating the DWA data words.

17. The circuit of claim 12 , further comprises a DWA circuit having an input receiving thermometer data words and an output generating DWA data words, wherein said first detector circuit is a control circuit of said DWA circuit configured to utilize the first bit location in selecting a starting bit location for the second string of logic 1 bits of the second DWA data word.

18. The circuit of claim 17 , wherein the first bit location and the starting hit location are a same bit location.

19. The circuit of claim 17 , wherein the DWA circuit comprises a crossbar switch matrix selectively coupling bits of each thermometer data word and bits of each DWA data word in response to said first bit location.

20. The circuit of claim 12 , further comprising:
a third detector circuit configured to identify whether all bits of said second DWA data word are logic 0; and
wherein said DWA-to-bin

Assignees

• St Microelectronics Int Nv

Inventors

• Bal Ankur
• Singh Rupesh

Classifications

• G06F5/015

  having at least two separately controlled shifting levels, e.g. using shifting matrices (G06F5/012 takes precedence) · CPC title

• H03M1/687

  Segmented, i.e. the more significant bit converter being of the unary decoded type and the less significant bit converter being of the binary weighted type · CPC title

• H03M1/662 Primary

  Multiplexed conversion systems · CPC title

• H03K3/356104

  using complementary field-effect transistors (H03K3/35625 takes precedence) · CPC title

• H03M7/04 Primary

  the radix thereof being two · CPC title