Control of skew between multiple data lanes

Patent metadata

Field	Value
Publication number	US-12463650-B2
Application number	US-202318348899-A
Country	US
Kind code	B2
Filing date	Jul 7, 2023
Priority date	Jul 28, 2022
Publication date	Nov 4, 2025
Grant date	Nov 4, 2025

Abstract

Provided are a method and apparatus for controlling a skew between multiple data lanes. In the method and apparatus, a first data lane control stage controls control outputting first data over a first data lane based on a first data lane clock and a second data lane control stage controls outputting second data over a second data lane based on a second data lane clock. In the method and apparatus, a first device is associated with a system clock and is configured to generate the first and second data for outputting over the first and second data lanes. A clock control stage causes the first and second data lane clocks to be offset from each other by a fixed time duration that is an integer fraction of a cycle duration of the system clock.

First claim

The invention claimed is:

1 . A system, comprising:
a first data lane control stage configured to:
control outputting first data over a first data lane based on a first data lane clock;
a second data lane control stage configured to:
control outputting second data over a second data lane based on a second data lane clock;
a first device associated with a system clock and configured to generate the first and second data for outputting over the first and second data lanes; and a clock control stage including:
a first flip-flop configured to:
generate a first data lane clock reset signal; and
output the first data lane clock reset signal to the first data lane control stage, the first data lane clock reset signal being operative to set a timing of the first data lane clock of the first data lane control stage; and

a second flip-flop configured to:
generate a second data lane clock reset signal that is offset from the first data lane clock reset signal a fixed time duration that is an integer fraction of a cycle duration of the system clock; and
output the second data lane clock reset signal to the second data lane control stage, the second data lane clock reset signal being operative to set a timing of the second data lane clock of the second data lane control stage.

2 . The system according to claim 1 , wherein the system clock is a symbol clock of the first device representing a duration time over which the first device outputs a symbol included in the first data or the second data.

3 . The system according to claim 1 , wherein the integer fraction is a reciprocal of a number of data lanes.

4 . The system according to claim 3 , wherein when a number of the data lanes is two, the fixed time duration is half the cycle duration of the system clock.

5 . The system according to claim 1 , wherein the clock control stage is configured to:
cause the first and second data lane clocks to be offset from each other by the fixed time duration by at least:
asserting the first data lane clock reset signal the fixed time duration after asserting the second data lane clock reset signal or asserting the second data lane clock reset signal the fixed time duration after asserting the second data lane clock reset signal.

6 . The system according to claim 5 , wherein the first data lane control stage is configured to generate the first data lane clock based on the first data lane clock reset signal, and the second data lane control stage is configured to generate the second data lane clock based on the second data lane clock reset signal.

7 . The system according to claim 5 , wherein:
the first flip-flop is configured to assert the first data lane clock reset signal at one of a falling edge or a rising edge of the system clock; and the second flip-flop is configured to assert the second data lane clock reset signal at another of the falling edge or the rising edge of the system clock.

8 . The system according to claim 5 , wherein the first data lane control stage is configured to reset a plurality of flip-flops of the first data lane control stage in response to the first data lane clock reset signal being asserted, and the second data lane control stage is configured to reset a plurality of flip-flops of the second data lane control stage in response to the second data lane clock reset signal being asserted.

9 . The system according to claim 1 , wherein a first serial clock has a first frequency that is an integer multiple of a frequency of the system clock and a second serial clock has a second frequency that is the integer multiple of the frequency of the system clock.

10 . The system according to claim 9 , wherein the first data lane control stage includes a first serializer configured to retrieve the first data from a first first-input first-output (FIFO) buffer serially at a rate of the first serial clock, the second data lane control stage includes a second serializer is configured to retrieve the second data from the a second FIFO buffer serially at a rate of the second serial clock, and the first device is configured to input symbols representing the first and second data into the first and second FIFOs, respectively, at a rate of the system clock.

11 . A device, comprising:
a first flip-flop configured to:
generate a first data lane clock reset signal; and
output the first data lane clock reset signal to a first data lane control stage, the first data lane clock reset signal being operative to set a timing of a first data lane clock of the first data lane control stage, the first data lane clock being used to control outputting first data over a first data lane; and
a second flip-flop configured to:
generate a second data lane clock reset signal that is offset from the first data lane clock reset signal by an integer fraction of a cycle duration of a system clock; and
output the second data lane clock reset signal to a second data lane control stage, the second data lane clock reset signal being operative to set a timing of a second data lane clock of the second data lane control stage, the second data lane clock being used to control outputting second data over a second data lane.

12 . The device according to claim 11 , wherein the system clock is a symbol clock of a first device representing a duration time over which the first device outputs a symbol included in the first data or the second data.

13 . The device according to claim 11 , wherein the integer fraction is a reciprocal of a number of data lanes.

14 . The device according to claim 13 , wherein when a number of the data lanes is two, the second data lane clock reset signal is offset from the first data lane clock reset signal by half the cycle duration of the system clock.

15 . The device according to claim 11 , wherein the first flip-flop is configured to assert the first data lane clock reset signal at one of a falling edge or a rising edge of the system clock and the second flip-flop configured to assert the second data lane clock reset signal at another of the falling edge or the rising edge of the system clock.

16 . The device according to claim 11 , wherein the first data lane control stage is configured to reset a plurality of flip-flops of the first data lane control stage in response to the first data lane clock reset signal being asserted, and the second data lane control stage is configured to reset a plurality of flip-flops of the second data lane control stage in response to the second data lane clock reset signal being asserted.

17 . The device according to claim 11 , wherein a first serial clock has a first frequency that is an integer multiple of a frequency of the system clock and a second serial clock has a second frequency that is the integer multiple of the frequency of the system clock.

18 . The device according to claim 17 , wherein the first data lane control stage includes a first serializer configured to retrieve the first data from a first first-input first-output (FIFO) buffer at a rate of the first serial clock, the second data lane control stage includes a second serializer configured to retrieve the second data from the a second FIFO buffer at a rate of the second serial clock, and a first device is configured to input symbols representing the first and second data into the first and second FIFOs, respectively, at a rate of the system clock.

19 . A method, comprising:
generating a first data lane clock reset signal; setting a timing of a first data lane clock based on the first data lane cloc

Assignees

• St Microelectronics Int Nv

Inventors

• Singh Rupesh
• Bal Ankur

Classifications

• H03L7/199

  with reset of the frequency divider or the counter, e.g. for assuring initial synchronisation · CPC title

• H03K3/356026

  with synchronous operation (H03K3/356034, H03K3/356052 take precedence) · CPC title

• G06F1/10

  Distribution of clock signals {, e.g. skew} · CPC title

• H03L7/195 Primary

  in which the counter of the loop counts between two different non zero numbers, e.g. for generating an offset frequency (H03L7/193 takes precedence) · CPC title

• H03K5/15 Primary

  Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors (distributing, switching or gating arrangements H03K17/00) · CPC title