Method for latency detection on a hardware simulation accelerator
US-11875095-B2 · Jan 16, 2024 · US
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Schumann John A patents
Schumann John A is listed as an inventor on 42 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Schumann John A |
| Total patents | 42 |
| First publication | Jun 22, 2017 |
| Latest publication | Jan 16, 2024 |
Notable patents
Publications ranked by popularity score, then publication date.
Un-mark instructions on an instruction match to reduce resources required to match a group of instructions
US-2023048717-A1 · Feb 16, 2023 · US
Obscuring information in virtualization environment
US-11556365-B2 · Jan 17, 2023 · US
Generating and adding additional control information to logic under test to facilitate debugging and comprehension of a simulation
US-11475191-B2 · Oct 18, 2022 · US
Method and system for detection of thread stall
US-11436013-B2 · Sep 6, 2022 · US
Processor performance monitor that logs reasons for reservation loss
US-11347505-B2 · May 31, 2022 · US
Address translation cache invalidation in a microprocessor
US-11301392-B2 · Apr 12, 2022 · US
Identifying translation errors
US-11243864-B2 · Feb 8, 2022 · US
Method for latency detection on a hardware simulation accelerator
US-2022004680-A1 · Jan 6, 2022 · US
Dynamic modification of instructions that do not modify the architectural state of a processor
US-11157285-B2 · Oct 26, 2021 · US
Recent patents
Latest publications not already listed above.
Performance benchmark generation
US-11138089-B2 · Oct 5, 2021 · US
Dynamic modification of instructions that do not modify the architectural state of a processor
US-2021247982-A1 · Aug 12, 2021 · US
Software-invisible interrupt for a microprocessor
US-11080122-B2 · Aug 3, 2021 · US
Obscuring information in virtualization environment
US-2021089340-A1 · Mar 25, 2021 · US
Software-invisible interrupt for a microprocessor
US-2021089382-A1 · Mar 25, 2021 · US
Identifying translation errors
US-2021081296-A1 · Mar 18, 2021 · US
System and method including broadcasting an address translation invalidation instruction with a return marker to indentify the location of data in a computing system having mutiple processors
US-10942853-B2 · Mar 9, 2021 · US
Address translation cache invalidation in a microprocessor
US-10915456-B2 · Feb 9, 2021 · US
Address translation cache invalidation in a microprocessor
US-2021019262-A1 · Jan 21, 2021 · US
Precise verification of a logic problem on a simulation accelerator
US-10896273-B2 · Jan 19, 2021 · US
Address translation cache invalidation in a microprocessor
US-2020371951-A1 · Nov 26, 2020 · US
Generating and adding additional control information to logic under test to facilitate debugging and comprehension of a simulation
US-2020364313-A1 · Nov 19, 2020 · US
Method and system for detection of thread stall
US-2020225952-A1 · Jul 16, 2020 · US
Method and system for detection of thread stall
US-10705843-B2 · Jul 7, 2020 · US
Performance benchmark generation
US-2020201739-A1 · Jun 25, 2020 · US
Data location identification
US-2020201767-A1 · Jun 25, 2020 · US
Processor performance monitor that logs reasons for reservation loss
US-2020150961-A1 · May 14, 2020 · US
Precise verification of a logic problem on a simulation accelerator
US-2020117766-A1 · Apr 16, 2020 · US
Processor performance monitor that logs reasons for reservation loss
US-10579376-B2 · Mar 3, 2020 · US
Circuit design verification in a hardware accelerated simulation environment using breakpoints
US-10539614-B2 · Jan 21, 2020 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| IBM | 42 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G06F30/33 | 11 |
| G06F9/3836 | 7 |
| G06F30/331 | 7 |
| G06F11/261 | 7 |
| G06F11/0721 | 6 |