Generating and adding additional control information to logic under test to facilitate debugging and comprehension of a simulation

Patent metadata

Field	Value
Publication number	US-11475191-B2
Application number	US-201916412688-A
Country	US
Kind code	B2
Filing date	May 15, 2019
Priority date	May 15, 2019
Publication date	Oct 18, 2022
Grant date	Oct 18, 2022

Abstract

Provided are systems, methods, and media for handling simulation of logic under test. An example method includes receiving a simulation model for the logic under test. Generating second logic that is configured to create a set of output logic signals based on an existing set of input logic signals of the logic under test. Rebuilding the simulation model based, at least in part, on the second logic. Examining a netlist of the rebuilt simulation model to identify the set of output logic signals created by the second logic. Generating during the execution of the simulation, a bus trace that is configured to capture at least the identified set of output logic signals.

First claim

What is claimed is:

1. A computer-implemented method for handling simulation of logic under test, the computer-implemented method comprising:
receiving, by a system comprising one or more processors, a simulation model for the logic under test;
identifying an existing set of input logic signals of the logic under test, the set of input logic signals including a first input logic signal;
generating, by the system, second logic that is configured to create a set of output logic signals based on the identified existing set of input logic signals of the logic under test, the set of output logic signals including a first output logic signal configured to generate a first valid state in response to the first input logical state being associated with a data beat and a second output logic signal configured to generate a second valid state in response to the first output logic signal being active, wherein the set of output logic signals created by the second logic includes a data packet start signal and a control not data signal, wherein the data packet start signal is valid when the data valid signal is associated with a first beat of a data packet, wherein the control not data signal is valid when the data packet start signal is active;
rebuilding, by the system, the simulation model based, at least in part, on the second logic;
examining, by the system, a netlist of the rebuilt simulation model to identify the set of output logic signals created by the second logic;
executing, by the system, a simulation based on the rebuilt simulation model; and
generating, by the system, during the execution of the simulation, a bus trace that is configured to capture at least the identified set of output logic signals,
wherein the existing set of input logic signals includes a data beat signal, a data valid signal, and a clock signal.

2. The computer-implemented method of claim 1 , wherein the generating of the second logic includes implementing a state-machine that is configured to track data beats of the data packet.

3. The computer-implemented method of claim 1 , wherein the generating of the bus trace comprises generating an All Events Trace (AET) for a system bus, wherein the method further comprises:
reading the identified signals that are captured by the AET for the system bus; and
decoding bus transactions of the system bus based on the reading.

4. The computer-implemented method of claim 3 further comprising:
presenting the decoded bus transactions as a text listing of bus activity to a user, wherein the test listing includes cycle times of the bus transactions taking place on the system bus.

5. The computer-implemented method of claim 1 , wherein the second logic is implemented as a VHDL wrapper.

6. A computer program product for handling simulation of logic under test, the computer program product comprising a non-transitory computer readable storage medium having program instructions embodied therewith, the program instructions executable by a system comprising one or more processors to cause the system to perform a method comprising:
receiving, by a system comprising one or more processors, a simulation model for the logic under test;
identifying an existing set of input logic signals of the logic under test, the set of input logic signals including a first input logic signal;
generating, by the system, second logic that is configured to create a set of output logic signals based on the identified existing set of input logic signals of the logic under test, the set of output logic signals including a first output logic signal configured to generate a first valid state in response to the first input logical state being associated with a data beat and a second output logic signal configured to a second valid state in response to the first output logic signal being active, wherein the set of output logic signals created by the second logic includes a data packet start signal and a control not data signal, wherein the data packet start
signal is valid when the data valid signal is associated with a first beat of a data packet, wherein the control not data signal is valid when the data packet start signal is active;
rebuilding, by the system, the simulation model based, at least in part, on the second logic;
examining, by the system, a netlist of the rebuilt simulation model to identify the set of output logic signals created by the second logic;
executing, by the system, a simulation based on the rebuilt simulation model; and
generating, by the system, during the execution of the simulation, a bus trace that is configured to capture at least the identified set of output logic signals,
wherein the existing set of input logic signals includes a data beat signal, a data valid signal, and a clock signal.

7. The computer program product of claim 6 , wherein the generating of the second logic includes implementing a state-machine that is configured to track data beats of the data packet.

8. The computer program product of claim 6 , wherein the generating of the bus trace comprises generating an All Events Trace (AET) for a system bus, wherein the method further comprises:
reading the identified signals that are captured by the AET for the system bus; and
decoding bus transactions of the system bus based on the reading.

9. The computer program product of claim 8 , wherein the method further comprises:
presenting the decoded bus transactions as a text listing of bus activity to a user, wherein the test listing includes cycle times of the bus transactions taking place on the system bus.

10. The computer program product of claim 6 , wherein the second logic is implemented as a VHDL wrapper.

11. A system for handling simulation of logic under test, the system comprising one or more processors configured to perform a method comprising:
receiving, by a system comprising one or more processors, a simulation model for the logic under test;
identifying an existing set of input logic signals of the logic under test, the set of input logic signals including a first input logic signal;
generating, by the system, second logic that is configured to create a set of output logic signals based on the identified existing set of input logic signals of the logic under test, the set of output logic signals including a first output logic signal configured to generate a first valid state in response to the first input logical state being associated with a data beat and a second output logic signal configured to a second valid state in response to the first output logic signal being active, wherein the set of output logic signals created by the second logic includes a data packet start signal and a control not data signal, wherein the data packet start
signal is valid when the data valid signal is associated with a first beat of a data packet, wherein the control not data signal is valid when the data packet start signal is active;
rebuilding, by the system, the simulation model based, at least in part, on the second logic;
examining, by the system, a netlist of the rebuilt simulation model to identify the set of output logic signals created by the second logic;
executing, by the system, a simulation based on the rebuilt simulation model; and
generating, by the system, during the execution of the simulation, a bus trace that is configured to capture at least the identified set of output logic signals,
wherein the existing set of input logic signals includes a data beat signal, a data valid signal, and a clock signal.

12. The system of claim 11 , wherein the generating of the second logic includes implementing a state-machine that is configured to track data beats of the data packe

Assignees

• IBM

Inventors

• Umbarger Paul
• Chatterjee Debapriya
• Yokum Karen
• Schumann John A
• Cockcroft Bryant
• Barnett Kevin

Classifications

• G06F30/327 Primary

  Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist · CPC title

• G06F30/33 Primary

  Design verification, e.g. functional simulation or model checking · CPC title