Address translation cache invalidation in a microprocessor

Patent metadata

Field	Value
Publication number	US-11301392-B2
Application number	US-202017063888-A
Country	US
Kind code	B2
Filing date	Oct 6, 2020
Priority date	May 21, 2019
Publication date	Apr 12, 2022
Grant date	Apr 12, 2022

Abstract

A method and an information handling system having a plurality of processors connected by a cross-processor network, where each of the plurality of processors preferably has a filter construct having an outgoing filter list that identifies logical partition identifications (LPIDs) that are exclusively assigned to that processor and/or an incoming filter list that identifies LPIDs on that processor and at least one additional processor in the system. In operation, if the LPID of the outgoing translation invalidation instruction is on the outgoing filter list, the address translation invalidation instruction is acknowledged on behalf of the system. If the LPID of the incoming invalidation instruction does not match any LPID on the incoming filter list, then the translation invalidation instruction is acknowledged, and if the LPID of the incoming invalidation instruction matches any LPID on the incoming filter list, then the invalidation instruction is sent into the respective processor.

First claim

What is claimed is:

1. A method of handling information in an information handling system having a plurality of processors connected by a cross-processor network, the method comprising:
issuing an address translation invalidation instruction having a logical partition identification (LPID) in one of the plurality of processors in the processing system;
checking an outgoing filter list in the processor where the address translation invalidation instruction issued, wherein the outgoing filter list identifies LPIDS that are exclusively assigned to that processor;
determining whether the LPID of the address translation invalidation instruction matches any of the LPIDs in the outgoing filter list; and
acknowledging, in at least partial response to the LPID of the address translation invalidation instruction matching any of the LPIDs in the outgoing filter list, the translation instruction invalidation instruction on behalf of the system.

2. The method of claim 1 , further comprising:
checking within the one or more translation buffers in the processor where the address translation invalidation instruction issues for address translation entries that correspond to the address translation invalidation instruction.

3. The method of claim 1 , further comprising:
sending, in response to the LPID of the address translation invalidation instruction not matching any of the LPIDs in the outgoing filter, the address translation invalidation instruction out of the processor where the address translation invalidation instruction issued to the other processors in the system.

4. The method of claim 1 , further comprising:
circulating the address translation invalidation instruction on the cross-processor network to send the address translation invalidation instruction to the processors in the system other than the processor where the address translation invalidation instruction issued.

5. The method of claim 1 , wherein each processor comprises a filter construct having the outgoing filter list and an incoming filter list that identifies the LPIDs assigned to that processor and at least one other processor in the system, the method further comprising:
determining, for each of the plurality of processors in the system other than the processor where the address translation invalidation instruction issued, whether the LPID of the address translation invalidation instruction matches any of the LPIDs in the respective processor incoming filter list; and
sending, in response to the LPID of the address translation invalidation instruction matching any of the LPIDs in the incoming filter list, the address translation invalidation instruction into that processor.

6. The method of claim 5 , further comprising:
checking, within a translation buffer in the processor where the LPID of the address translation invalidation instruction matches a LPID in the incoming filter list, for address translation entries that correspond to the address translation invalidation instruction; and
acknowledging, in response to completing the check within each processor that has a LPID in their incoming filter list that matches the LPID of the address translation invalidation instruction, the address translation invalidation instruction on behalf of the respective processor.

7. The method of claim 5 , further comprising:
acknowledging, in response to the LPID of the address translation invalidation instruction not matching any of the LPIDs in the incoming filter list, the address translation invalidation instruction on behalf of the respective processor.

8. The method of claim 5 , further comprising:
checking, within a translation buffer in the processor where the LPID of the address translation invalidation instruction matches a LPID in the incoming filter list, for address translation entries that correspond to the address translation invalidation instruction;
acknowledging, in response to completing the check within each processor that has a LPID in their incoming filter list that matches the LPID of the address translation invalidation instruction, the address translation invalidation instruction on behalf of the respective processor;
acknowledging, in response to the LPID of the address translation invalidation instruction not matching any of the LPIDs in the incoming filter list, the address translation invalidation instruction on behalf of the respective processor.

9. The method of claim 5 , further comprising updating and maintaining the outgoing and incoming filter lists using software.

10. The method of claim 5 , wherein the filter construct is on a network adapter that connects each of the processors to the cross-processor network.

11. A method of handling information in a system having a plurality of processors connected by a cross-processor network, the method comprising:
issuing an address translation invalidation instruction in one of the plurality of processors in the processing system;
sending the address translation invalidation instruction out of the processor where the address translation invalidation instruction issued to the other processors in the system;
determining, for each of the processors in the system other than the processor where the address translation invalidation instruction issued, whether the logical partition identification (LPID) of the address translation invalidation instruction matches any of the LPIDs in an incoming filter list of the respective processor, wherein the incoming filter list identifies LPIDs assigned to that processor and at least one other processor in the system; and
sending, in response to the LPID of the address translation invalidation instruction matching any of the LPIDs in the incoming filter list, the address translation invalidation instruction into the processor that has the matching LPID on the incoming filter list.

12. The method of claim 11 , further comprising:
checking, within a translation buffer in the processor where the LPID of the address translation invalidation instruction matches a LPID on the incoming filter list, for address translation entries that correspond to the address translation invalidation instruction; and
acknowledging, in response to completing the check within each processor that has a LPID in their incoming filter list that matches the LPID of the address translation invalidation instruction, the address translation invalidation instruction on behalf of the respective processor.

13. The method of claim 11 , further comprising:
acknowledging, in response to the LPID of the address translation invalidation instruction not matching any of the LPIDs in the incoming filter list, the address translation invalidation instruction on behalf of the respective processor.

14. The method of claim 11 , further comprising:
checking, within a translation buffers in the processor where the LPID of the address translation invalidation instruction matches a LPID in the incoming filter list, for address translation entries that correspond to the address translation invalidation instruction;
acknowledging, in response to completing the check within each processor that has a LPID in their incoming filter list that matches the LPID of the address translation invalidation instruction, the address translation invalidation instruction on behalf of the respective processor;
acknowledging, in response to the LPID of the address translation invalidation instruction not matching any of the LPIDs in the incoming filter list, the address translation invalidation instruction on behalf of the respective processor.

15. The method of claim 11 , further comprising:
checking wit

Assignees

• IBM

Inventors

• Chatterjee Debapriya
• Cockcroft Bryant
• Leitner Larry
• Schumann John A
• Yokum Karen

Classifications

• G06F12/1036

  for multiple virtual address spaces, e.g. segmentation (G06F12/1045 takes precedence) · CPC title

• G06F2212/657

  Virtual address space management · CPC title

• G06F2212/1024

  Latency reduction · CPC title

• G06F12/1027 Primary

  using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] · CPC title

• G06F12/10 Primary

  Address translation · CPC title