Dynamic modification of instructions that do not modify the architectural state of a processor

Patent metadata

Field	Value
Publication number	US-11157285-B2
Application number	US-202016783347-A
Country	US
Kind code	B2
Filing date	Feb 6, 2020
Priority date	Feb 6, 2020
Publication date	Oct 26, 2021
Grant date	Oct 26, 2021

Abstract

A system and method including a processor configured to, based on encountering an instruction that does not modify the architectural state of the processor, preferably a prefetch instruction, that is being executed by the processor, determine whether utilization of a first queue used in processing the instruction is over a first queue utilization limit; in response to the first queue utilization being over the first queue utilization limit, do not execute the prefetch instruction; and in response to the first queue utilization being under the first queue utilization limit, at least partially process the prefetch instruction.

First claim

What is claimed is:

1. A system, comprising a processor configured to:
based on encountering a prefetch instruction that is being executed by the processor:
determine whether utilization of a first queue used in processing the prefetch instruction is over a first queue utilization limit;
in response to the first queue utilization being over the first queue utilization limit, do not execute the prefetch instruction;
in response to the first queue utilization being under the first queue utilization limit, at least partially process the prefetch instruction;
based on the first queue utilization being under the first queue utilization limit, determine whether utilization of a second queue used in processing the prefetch instruction is over a second queue utilization limit;
in response to the second queue utilization being over the second queue utilization limit, do not further execute the prefetch instruction; and
in response to the second queue utilization being under the second queue utilization limit, at least partially further process the prefetch instruction.

2. The system of claim 1 , wherein in response to the first queue utilization being over the first queue utilization limit, mark the prefetch instruction complete notwithstanding that the prefetch instruction is not executed.

3. The system of claim 1 , wherein the prefetch instruction is a translation prefetch instruction in software.

4. The system of claim 1 , wherein the processor is further configured to:
based on the second queue utilization being under the second queue utilization limit, determine whether utilization of a third queue used in processing the prefetch instruction is over a third queue utilization limit;
in response to the third queue utilization being over the third queue utilization limit, do not further execute the prefetch instruction; and
in response to the third queue utilization being under the third queue utilization limit, at least partially further process the prefetch instruction.

5. The system of claim 1 , wherein the first queue is a load queue.

6. The system of claim 1 , wherein the second queue is at least one of the group comprising a translation queue and a load-miss queue.

7. The system of claim 1 , wherein the processor is further configured to, in response to the first queue utilization being equal to the first utilization limit, not execute the prefetch instruction.

8. A computer-implemented method, comprising:
based on encountering an instruction that does not modify the architectural state of a processor that is being executed by the processor:
determine, by the processor, whether a first performance criteria used in processing the instruction is over a first performance threshold;
in response to the first performance criteria being over the first performance threshold, do not execute the instruction;
in response to the first performance criteria being under the first performance threshold, at least partially process the instruction;
based on the first performance criteria being under the first performance threshold, determine whether a second performance criteria used in processing the instruction is over a second performance threshold;
in response to the second performance criteria being over the second performance threshold, do not further execute the instruction; and
in response to the second performance criteria being under the second performance threshold, at least partially further process the instruction.

9. The computer-implemented method of claim 8 , wherein the instruction that does not modify the architectural state of the processor is at least one of the group consisting of a prefetch instruction, a cache management instruction, and combinations thereof.

10. The computer-implemented method of claim 8 , further comprising in response to the first performance criteria being over the first performance threshold, mark the instruction complete notwithstanding that the instruction is not executed.

11. The computer-implemented method of claim 8 , wherein the first performance criteria is at least one of the group comprising: how full at least one queue is that is used to process the instruction, load bandwidth, processor power utilization, the frequency at which the instruction increases performance, and combinations thereof.

12. The computer-implemented method of claim 8 , wherein the instruction is a translation prefetch instruction and the first performance criteria is at least one of the group comprising utilization of a load queue, utilization of a translation queue, utilization of a load-miss queue, and combinations thereof.

13. The computer-implemented method of claim 8 , further comprising:
based on the second performance criteria being under the second performance threshold, determine whether a third performance criteria used in processing the instruction is over a third performance threshold;
in response to the third performance criteria being over the third performance threshold, do not further execute the instruction; and
in response to the third performance criteria being under the third performance threshold, at least partially further process the instruction.

14. An apparatus, comprising hardware logic configured to:
based on encountering a prefetch instruction that is being executed by the processor:
determine whether utilization of a first queue used in processing the prefetch instruction is over a first queue utilization limit;
in response to the first queue utilization being over the first queue utilization limit, do not execute the prefetch instruction;
based on determining the first queue utilization is under the first queue utilization limit, determine whether utilization of a second queue used in processing the instruction is over a second queue utilization limit;
in response to the second queue utilization being over the second queue utilization limit, do not further execute the instruction; and
in response to the second queue utilization being under the second queue utilization limit, at least partially further process the instruction.

15. The apparatus of claim 14 , wherein the hardware logic is configured to: in response to the first queue utilization being over the first queue utilization limit, mark the prefetch instruction complete notwithstanding that the prefetch instruction is not executed.

16. The apparatus of claim 14 , wherein the hardware logic is configured to process the prefetch instruction and the prefetch instruction is a translation prefetch instruction in software.

17. The apparatus of claim 16 , wherein the first queue utilization is at least one of the group comprising utilization of a load queue, utilization of a translation queue, utilization of a load-miss queue, and combinations thereof.

18. The apparatus of claim 14 , wherein the hardware logic is configured to:
based on the second queue utilization being under the second queue utilization limit, determine whether utilization of a third queue used in processing the instruction is over a third queue utilization limit;
in response to the third queue utilization being over the third queue utilization limit, do not further execute the instruction; and
in response to the third queue utilization being under the third queue limit, at least partially further process the instruction.

Assignees

• IBM

Inventors

• Cockcroft Bryant
• Schumann John A
• Yokum Karen
• Britto Vivek
• Chatterjee Debapriya

Classifications

• G06F2212/6028

  Prefetching based on hints or prefetch instructions · CPC title

• G06F12/0862

  with prefetch · CPC title

• G06F9/3836

  Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution · CPC title

• G06F9/3814 Primary

  Implementation provisions of instruction buffers, e.g. prefetch buffer; banks · CPC title

• G06F9/30047 Primary

  Prefetch instructions; cache control instructions · CPC title