Method and system for detection of thread stall

Patent metadata

Field	Value
Publication number	US-11436013-B2
Application number	US-202016831055-A
Country	US
Kind code	B2
Filing date	Mar 26, 2020
Priority date	Dec 21, 2017
Publication date	Sep 6, 2022
Grant date	Sep 6, 2022

Abstract

A method of checking for a stall condition in a processor is disclosed, the method including inserting an inline instruction sequence into a thread, the inline instruction sequence configured to read the result from a timing register during processing of a first instruction and store the result in a first general purpose register, wherein the timing register functions as a timer for the processor; and read the results from the timing register during processing of a second instruction and store the results in a second general purpose register, wherein the second instruction is the next consecutive instruction after the first instruction. The inline thread sequence may be inserted in sequence with the thread and further configured to compare the difference between the result in the first and second general purpose register to a programmable threshold.

First claim

What is claimed is:

1. A method of checking for a stall condition in a processor comprising:
providing an inline instruction sequence configured to: read a result from a timing register during processing of a first instruction, wherein the timing register functions as a timer for the processor, read the results from the timing register during processing of a second instruction, and determine a difference between the result read from the timing register during processing of the first instruction and the result read from the timing register during processing of the second instruction;
inserting the inline instruction sequence into a thread of instructions; and
executing the thread of instructions with the inserted inline instruction sequence,
wherein executing the thread of instructions with the inserted inline instruction sequence comprises:
reading the result from a timing register during processing of a first instruction,
reading the result from the timing register during processing of a second instruction,
determining a difference between the result read from the timing register of the first instruction and the result read during processing of the second instruction, and
using the difference to determine if there is a stall condition in the processor.

2. The method of claim 1 , wherein the inline instruction sequence is further configured to:
store the result read from the timing register during processing of the first instruction into a first register;
store the result read from the timing register during processing of the second instruction into a second resister;
subtract the result in the first general purpose register from the result in the second general purpose register and obtain a subtraction result;
store the value of the subtraction result in a third general purpose register; and
compare the value stored in the third general purpose register to a threshold.

3. The method of claim 2 , wherein the threshold is variable and programmable.

4. The method of claim 1 , wherein executing the thread of instructions with the inserted inline instruction sequence comprises comparing the difference between the result read from the timing register during processing of the first instruction to the result read from the timing register during processing of the second instruction; and using the comparison to determine if there is a stall condition in the processor.

5. The method of claim 1 , wherein executing the thread of instructions with the inserted inline instruction sequence comprises reading the result from the timing register during processing of the first instruction in the inline instruction sequence and storing the result in a first register; and reading the results from the timing register during processing of the second instruction in the inline sequence and storing the result in a second register.

6. The method of claim 5 , wherein the second instruction is the next consecutive instruction after the first instruction.

7. The method of claim 5 , wherein executing the thread of instructions with the inserted inline instruction sequence comprises subtracting the result of the first register from the result of the second register to obtain a subtraction result and comparing the subtraction result to a threshold.

8. The method of claim 7 , further comprising storing the subtraction result in a third register, and subtracting the subtraction result in the third register from the threshold.

9. The method of claim 8 , further comprising sending a signal to the processor that the thread has stalled if subtracting the subtraction result in the third register from the threshold results in a positive number.

10. The method of claim 1 , wherein the in-line instruction sequence is inserted into the thread in at least one of the group consisting of at the thread start up, at a performance sensitive area of the thread, and combinations thereof.

11. The method of claim 1 , wherein the timing register is the timebase register.

12. The method of claim 1 , wherein the inline instruction sequence is inserted in a first thread and used to determine a stall condition in a second, different thread.

13. The method of claim 1 performed by software.

14. A method of determining if a thread has stalled in a processor, the thread comprising a plurality of instructions, the method comprising:
inserting an inline instruction sequence into the thread;
executing the thread with the inserted inline instruction sequence;
determining the amount of time a processor undergoes to complete the inline instruction sequence;
comparing the amount of time to complete the inline instruction sequence to a threshold; and
using the comparison to determine if the thread has stalled in the processor.

15. The method of claim 14 , wherein executing the thread with the inserted inline sequence comprises:
reading a first result from a timing register during processing of a first instruction in the inline instruction sequence;
reading a second result from the timing register during processing of a second instruction in the inline instruction sequence.

16. The method of claim 15 , wherein determining the amount of time a processor undergoes to complete the inline instruction sequence comprises subtracting the first result from the second result to obtain a subtraction result.

17. The method of claim 16 , wherein comparing the amount of time to complete the inline instruction sequence comprises subtracting the subtraction result from the threshold, and using the comparison to determine if the thread has stalled in the processor comprises sending a signal indicating that the processor has stalled if subtracting the subtraction result from the threshold is a positive number.

18. A computer program product for checking for stalls in a pipeline of a processor, the computer program product comprising a computer readable storage medium having program instructions embedded therewith, the program instructions configurable as an in-line instruction sequence to be added to a thread and executable by a processor to cause the processor to:
read a first result from a timebase register during processing of a first instruction of the thread;
read a second result from the timebase register during processing of a second, consecutive instruction of the thread;
determine a difference in value between the second result and the first result, and
compare the difference to a threshold to determine whether there is a stall in the processor.

Assignees

• IBM

Inventors

• Bajaj Omesh
• Barnett Kevin
• Chatterjee Debapriya
• Cockcroft Bryant
• Hawkins Jamory
• Hehenberger Lance G
• Kellington Jeffrey
• Lecocq Paul
• Leitner Lawrence
• Pindicura Tharunachalam
• Schumann John A
• Umbarger Paul K
• Yokum Karen

Classifications

• G06F9/3869

  Implementation aspects, e.g. pipeline latches; pipeline synchronisation and clocking · CPC title

• G06F11/07

  Responding to the occurrence of a fault, e.g. fault tolerance · CPC title

• G06F11/0721

  within a central processing unit [CPU] · CPC title

• G06F11/00

  Error detection; Error correction; Monitoring (error detection, correction or monitoring in information storage based on relative movement between record carrier and transducer G11B20/18; monitoring, i.e. supervising the progress of recording or reproducing G11B27/36; in static stores G11C29/00) · CPC title

• G06F9/30098

  Register arrangements · CPC title