Software-invisible interrupt for a microprocessor

Patent metadata

Field	Value
Publication number	US-11080122-B2
Application number	US-201916575697-A
Country	US
Kind code	B2
Filing date	Sep 19, 2019
Priority date	Sep 19, 2019
Publication date	Aug 3, 2021
Grant date	Aug 3, 2021

Abstract

Examples described herein provide a computer-implemented method that includes executing, by the microprocessor, instructions in an instruction stream of the microprocessor. The method further includes triggering, by control logic of the microprocessor, error condition monitoring logic. The method further includes executing, by the error condition monitoring logic of the microprocessor, an error instruction stream built into the microprocessor to break the microprocessor out of an error condition.

First claim

What is claimed is:

1. A computer-implemented method for invisible interrupt of a microprocessor, the method comprising:
executing, by the microprocessor, instructions in an instruction stream of the microprocessor;
triggering, by control logic of the microprocessor, error condition monitoring logic wherein the error condition monitoring logic is triggered randomly; and
executing, by the error condition monitoring logic of the microprocessor, an error instruction stream built into the microprocessor to break the microprocessor out of an error condition.

2. The computer-implemented method of claim 1 , wherein executing the error instruction stream does not change an architectural state of the microprocessor.

3. The computer-implemented method of claim 1 , further comprising:
subsequent to breaking the microprocessor out of the error condition, continuing executing the instructions in the instruction stream of the microprocessor.

4. The computer-implemented method of claim 1 , wherein the microprocessor comprises an arithmetic logic unit and a register.

5. A microprocessor comprising:
an instruction stream for executing instructions;
control logic for triggering an error condition monitoring logic, wherein the error condition monitoring logic is triggered randomly; and
the error condition monitoring logic for executing an error instruction stream built into the microprocessor to break the microprocessor out of an error condition.

6. The microprocessor of claim 5 , wherein executing the error instruction stream does not change an architectural state of the microprocessor.

7. The microprocessor of claim 5 , wherein the instruction stream continues to execute the instructions in the instruction stream of the microprocessor subsequent to breaking the microprocessor out of the error condition.

8. The microprocessor of claim 5 , further comprising:
an arithmetic logic unit; and
a register.

Assignees

• IBM

Inventors

• Leitner Larry
• Schumann John A
• Chatterjee Debapriya
• Sharp Wallace
• Cockcroft Bryant

Classifications

• G06F11/0793

  Remedial or corrective actions (recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40) · CPC title

• G06F11/0721

  within a central processing unit [CPU] · CPC title

• G06F11/0772 Primary

  Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers · CPC title

• G06F9/4812

  by interrupt, e.g. masked · CPC title