Method for latency detection on a hardware simulation accelerator

Patent metadata

Field	Value
Publication number	US-11875095-B2
Application number	US-202016918675-A
Country	US
Kind code	B2
Filing date	Jul 1, 2020
Priority date	Jul 1, 2020
Publication date	Jan 16, 2024
Grant date	Jan 16, 2024

Abstract

A method for performing automated detection of transaction latency for a processor design model running an application in a hardware simulation accelerator. The method includes loading the processor design model into the hardware simulation accelerator, loading the application into the processor design model running within the hardware simulation accelerator, simulating the processor design model running the application within the hardware simulation accelerator, and for each individual transaction of the application: establishing a first checkpoint at a start of an execution of the individual transaction by creating a breakpoint and resetting a counter, establishing a second checkpoint at a completion of the transaction by creating another breakpoint and obtaining latency information for the second checkpoint. The latencies of the individual transaction from the start to the completion are measured based on the latency information.

First claim

What is claimed is:

1. A computer-implemented method comprising:
simulating a processor design model running an application within a hardware simulation accelerator, the hardware simulation accelerator comprising a plurality of application-specific integrated circuit processors, the processor design model comprising a plurality of logic gates represented using a hardware description language, the application comprising a plurality of transactions, the application loaded into a memory of the hardware simulation accelerator, the simulating comprising simulating, using the plurality of application-specific integrated circuit processors, execution of the plurality of logic gates;
setting a previous measured latency to a target latency value; and
for each individual transaction of the application:
generating, by the hardware simulation accelerator at a start of an execution of the individual transaction, a first checkpoint file, the first checkpoint file comprising data of a meta state of the processor design model at said start, wherein the first checkpoint file comprises a value of a counter at said start;
generating, by the hardware simulation accelerator at a completion of the individual transaction, a second checkpoint file, the second checkpoint file comprising data of the meta state of the processor design model at said completion, wherein the second checkpoint file comprises a value of the counter, wherein the simulating continues after generating the second checkpoint file;
measuring, by a software checker using the first checkpoint file and the second checkpoint file, a latency of said individual transaction from said start to said completion;
deleting, responsive to determining that the measured latency is less than or equal to the previous measured latency, the first checkpoint file and the second checkpoint file;
replacing, responsive to determining that the measured latency is greater than the previous measured latency, the previous measured latency with the measured latency, the replacing comprising saving the first checkpoint file and the second checkpoint file; and

deleting, subsequent to measuring a latency of each individual transaction of the application, a first checkpoint file and a second checkpoint file corresponding to a measured latency that is less than a maximum measured latency.

2. The method according to claim 1 , wherein the target latency value is based on an existing idle latency test.

3. The method according to claim 2 , wherein the target latency value is a defined percentage below a performance latency result per transaction of said existing idle latency test.

4. The method according to claim 1 , wherein the replacing is performed responsive to determining that the measured latency is a defined percentage above the previous measured latency.

5. The method according to claim 1 , wherein said latency is measured in processor clock cycles taken to complete the individual transaction.

6. The method according to claim 1 wherein the application is a workload software application or an exerciser.

7. A non-transitory computer-readable storage medium, the computer-readable storage medium including instructions that when executed by a computer, cause the computer to:
simulate a processor design model running an application within a hardware simulation accelerator, the hardware simulation accelerator comprising a plurality of application-specific integrated circuit processors, the processor design model comprising a plurality of logic gates represented using a hardware description language, the application comprising a plurality of transactions, the application loaded into a memory of the hardware simulation accelerator, the simulating comprising simulating, using the plurality of application-specific integrated circuit processors, execution of the plurality of logic gates;
set a previous measured latency to a target latency value; and
for each individual transaction of the application:
generate, by the hardware simulation accelerator at a start of an execution of the individual transaction, a first checkpoint file, the first checkpoint file comprising data of a meta state of the processor design model at said start, wherein the first checkpoint file comprises a value of a counter at said start;
generate, by the hardware simulation accelerator at a completion of the individual transaction, a second checkpoint file, the second checkpoint file comprising data of the meta state of the processor design model at said completion, wherein the second checkpoint file comprises a value of the counter, wherein the simulating continues after generating the second checkpoint file;
measure, by a software checker using the first checkpoint file and the second checkpoint file, a latency of said individual transaction from said start to said completion;
delete, responsive to determining that the measured latency is less than or equal to the previous measured latency, the first checkpoint file and the second checkpoint file;
replace, responsive to determining that the measured latency is greater than the previous measured latency, the previous measured latency with the measured latency, the replacing comprising saving the first checkpoint file and the second checkpoint file; and
delete, subsequent to measuring a latency of each individual transaction of the application, a first checkpoint file and a second checkpoint file corresponding to a measured latency that is less than a maximum measured latency.

8. A computer system, the computer system comprising:
a processor; and
a memory storing instructions that, when executed by the processor, configure the computer system to:
simulate a processor design model running an application within a hardware simulation accelerator, the hardware simulation accelerator comprising a plurality of application-specific integrated circuit processors, the processor design model comprising a plurality of logic gates represented using a hardware description language, the application comprising a plurality of transactions, the application loaded into a memory of the hardware simulation accelerator, the simulating comprising simulating, using the plurality of application-specific integrated circuit processors, execution of the plurality of logic gates;
set a previous measured latency to a target latency value; and
for each individual transaction of the application:
generate, by the hardware simulation accelerator at a start of an execution of the individual transaction, a first checkpoint file, the first checkpoint file comprising data of a meta state of the processor design model at said start, wherein the first checkpoint file comprises a value of a counter at said start;
generate, by the hardware simulation accelerator at a completion of the individual transaction, a second checkpoint file, the second checkpoint file comprising data of the meta state of the processor design model at said completion, wherein the second checkpoint file comprises a value of the counter, wherein the simulating continues after generating the second checkpoint file;
measure, by a software checker using the first checkpoint file and the second checkpoint file, a latency of said individual transaction from said start to said completion;
delete, responsive to determining that the measured latency is less than or equal to the previous measured latency, the first checkpoint file and the second checkpoint file;
replace, responsive to determining that the measured latency is greater than the previous measured latency, the previous measured latency with the measured latency, the replacing comprising saving the first checkpoint file and the second checkpoint file; and

delete, subsequent to measuring a latency of each individual tran

Assignees

• IBM

Inventors

• Schumann John A
• Pindicura Tharunachalam
• Srivatsan Shricharan
• Britto Vivek
• Venkataraman Madhumitha

Classifications

• G06F30/20 Primary

  Design optimisation, verification or simulation (optimisation, verification or simulation of circuit designs G06F30/30) · CPC title

• G06F9/445

  Program loading or initiating (bootstrapping G06F9/4401; security arrangements for program loading or initiating G06F21/57) · CPC title

• G06F9/455

  Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines · CPC title

• G06F2115/10

  Processors · CPC title

• G06F30/331 Primary

  with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation · CPC title