Identifying translation errors

Patent metadata

Field	Value
Publication number	US-11243864-B2
Application number	US-201916572855-A
Country	US
Kind code	B2
Filing date	Sep 17, 2019
Priority date	Sep 17, 2019
Publication date	Feb 8, 2022
Grant date	Feb 8, 2022

Abstract

An instruction may be associated with a memory address. During execution of the instruction, the memory address may be translated to a next level memory address. The instruction may also be marked for address tracing. If the instruction is marked for address tracing, then during execution of the instruction, the memory address and the next level memory address may be recorded.

First claim

What is claimed is:

1. A method, comprising:
determining that an instruction is marked for address tracing, wherein the instruction is stored at a first memory address;
disabling, responsive to a determination that the instruction is marked for address tracing, cache lookup and translation lookaside buffer lookup for the instruction;
executing, responsive to the determination, the instruction, wherein the executing includes translating a second memory address associated with the instruction from a first level address to a second level address; and
recording, responsive to the determination, the first level address and the second level address.

2. The method of claim 1 , wherein:
the executing further includes translating the second level address to a third level address; and
the method further comprises recording, responsive to the determination that the instruction is marked for address tracing, the third level address.

3. The method of claim 2 , wherein:
the third level address is a machine memory address;
the second level address is a guest physical memory address; and
the first level address is a guest virtual memory address.

4. The method of claim 1 , further comprising:
comparing the first level address to a first expected address; and
comparing the second level address to a second expected address.

5. The method of claim 4 , further comprising outputting a result of the comparisons.

6. The method of claim 1 , further comprising triggering an interrupt after recording at least one of the first address and the second address.

7. The method of claim 1 , further comprising writing the first level address and the second level address to a memory, wherein recording the first level address and the second level address comprises recording the first level address and the second level address in an array.

8. The method of claim 1 , further comprising triggering an interrupt.

9. A system, comprising:
a memory; and
a processor coupled to the memory, the processor configured to:
determine that an instruction is marked for address tracing, wherein the instruction is stored at a first memory address;
disable, responsive to a determination that the instruction is marked for address tracing, cache lookup and translation lookaside buffer lookup for the instruction;
execute, responsive to the determination, the instruction, wherein the executing includes translating a second memory address associated with the instruction from a first level address to a second level address; and
record, responsive to the determination, the first level address and the second level address.

10. The system of claim 9 , wherein:
the executing further includes translating the second level address to a third level address; and
the processor is further configured to record, responsive to the determination that the instruction is marked for address tracing, the third level address.

11. The system of claim 10 , wherein:
the third level address is a machine memory address;
the second level address is a guest physical memory address; and
the first level address is a guest virtual memory address.

12. The system of claim 9 , wherein the processor is further configured to:
compare the first level address to a first expected address; and
compare the second level address to a second expected address.

13. The system of claim 9 , wherein the processor is further configured to output a result of the comparisons.

14. The system of claim 9 , wherein the processor is further configured to write the first level address and the second level address to the memory, wherein recording the first level address and the second level address comprises recording the first level address and the second level address in an array.

15. The system of claim 9 , wherein the processor is further configured to trigger an interrupt.

16. A computer program product, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a computer to cause the computer to:
determine that an instruction is marked for address tracing, wherein the instruction is stored at a first memory address;
disable, responsive to a determination that the instruction is marked for address tracing, cache lookup and translation lookaside buffer lookup for the instruction;
execute, responsive to the determination, the instruction, wherein the executing includes translating a second memory address associated with the instruction from a first level address to a second level address; and
record, responsive to the determination, the first level address and the second level address.

17. The computer program product of claim 16 , wherein the instructions further cause the computer to:
compare the first level address to a first expected address; and
compare the second level address to a second expected address.

18. The computer program product of claim 16 , wherein the instructions further cause the computer to write the first level address and the second level address to a memory, wherein recording the first level address and the second level address comprises recording the first level address and the second level address in an array.

Assignees

• IBM

Inventors

• Cockcroft Bryant
• Schumann John A
• Chatterjee Debapriya
• Leitner Larry
• Barnett Kevin
• Yokum Karen

Classifications

• G06F11/3471 Primary

  Address tracing · CPC title

• G06F2212/1016

  Performance improvement · CPC title

• G06F9/4812

  by interrupt, e.g. masked · CPC title

• G06F11/073 Primary

  in a memory management context, e.g. virtual memory or cache management (memory management G06F12/00; testing of static memory units G11C29/00) · CPC title

• G06F12/0888

  using selective caching, e.g. bypass · CPC title