Processor performance monitor that logs reasons for reservation loss

Patent metadata

Field	Value
Publication number	US-10579376-B2
Application number	US-201615212146-A
Country	US
Kind code	B2
Filing date	Jul 15, 2016
Priority date	Jul 15, 2016
Publication date	Mar 3, 2020
Grant date	Mar 3, 2020

Abstract

A processor includes a performance monitor that logs reservation losses, and additionally logs reasons for the reservation losses. By logging reasons for the reservation losses, the performance monitor provides data that can be used to determine whether the reservation losses were due to valid programming, such as two threads competing for the same lock, or whether the reservation losses were due to bad programming. When the reservation losses are due to bad programming, the information can be used to improve the programming to obtain better performance.

First claim

The invention claimed is:

1. An integrated circuit processor comprising:
a performance monitor that detects and logs a plurality of reservation losses in the processor, wherein for a selected one of the plurality of reservation losses, the performance monitor samples less than all addresses that correspond to the selected one reservation loss, and additionally determines and logs a reason for the one selected reservation loss at each sampled address, wherein the reason comprises a bit, wherein a first value of the bit indicates a bad programming reason for the selected one reservation loss at the sampled address and a second value of the bit indicates a valid programming reason for the selected one reservation loss at the sampled address.

2. The processor of claim 1 wherein a reservation loss occurs between a first instruction that gains a reservation on a specified memory address and a second instruction that completes operations on the specified memory address.

3. The processor of claim 2 wherein the first instruction comprises a Load and Reserve Indexed (larx) instruction and the second instruction comprises a Store Conditional Indexed (stcx) instruction defined in an instruction set for a PowerPC processor.

4. The processor of claim 2 wherein a reservation for the specified memory address comprises a reservation for a cache line that includes the specified memory address.

5. The processor of claim 4 wherein the reservation for the cache line is lost when a store is made to a second memory address in the cache line after the first instruction is executed by the processor and before the second instruction is executed by the processor.

6. The processor of claim 1 wherein the processor further comprises:
a cache memory that includes a plurality of cache lines, wherein a reservation for a specified memory address comprises a reservation for a cache line that includes the specified memory address; and
a load/store unit that indicates to the performance monitor when a reservation loss is due to a store to the cache line that includes the specified memory address.

7. The processor of claim 1 wherein the performance monitor comprises a plurality of reservation loss counters, wherein a first of the plurality of reservation loss counters is incremented when the selected one reservation loss is due to bad programming and a second of the plurality of reservation loss counters is incremented when the selected one reservation loss is due to valid programming.

8. The processor of claim 1 wherein the performance monitor comprises a plurality of reservation loss counters, wherein a first plurality of the plurality of reservation loss counters each corresponds to a different bad programming reason for reservation loss, wherein when the selected one reservation loss is due to bad programming, the performance monitor increments one of the first plurality of reservation loss counters corresponding to a bad programming reason for the selected one reservation loss, wherein the performance monitor further comprises a different reservation loss counter not in the first plurality of the plurality of reservation loss counters, wherein the performance monitor increments the different reservation loss counter when the selected one reservation loss is due to valid programming.

9. A method for logging reservation losses in an integrated circuit processor, the method comprising:
detecting a plurality of reservation losses in the processor;
logging the plurality of reservation losses;
selecting one of the plurality of reservation losses;
sampling less than all addresses that correspond to the selected one reservation loss;
determining a reason for the one selected reservation loss at each sampled address;
and
logging the reason for the one selected reservation loss at each sampled address, wherein the reason comprises a bit, wherein a first value of the bit indicates a bad programming reason for the selected one reservation loss at the sampled address and a second value of the bit indicates a valid programming reason for the selected one reservation loss at the sampled address.

10. The method of claim 9 wherein a reservation loss occurs between a first instruction that gains a reservation on a specified memory address and a second instruction that completes operations on the specified memory address.

11. The method of claim 10 wherein the first instruction comprises a Load and Reserve Indexed (larx) instruction and the second instruction comprises a Store Conditional Indexed (stcx) instruction defined in an instruction set for a PowerPC processor.

12. The method of claim 10 wherein a reservation for the specified memory address comprises a reservation for a cache line that includes the specified memory address.

13. The method of claim 12 wherein the reservation for the cache line is lost when a store is made to a second memory address in the cache line after the first instruction is executed by the processor and before the second instruction is executed by the processor.

14. The method of claim 9 wherein a reservation for a specified memory address comprises a reservation for a cache line that includes the specified memory address, the method further comprising:
a load/store unit in the processor indicating when a reservation loss is due to a store to the cache line that includes the specified memory address.

15. The method of claim 9 wherein the reason is indicated in a plurality of reservation loss counters, the method further comprising:
incrementing a first of the plurality of reservation loss counters when a selected reservation loss is due to bad programming; and
incrementing a second of the plurality of reservation loss counters when the selected reservation loss is due to valid programming.

16. The method of claim 9 wherein the reason is indicated in a plurality of reservation loss counters, wherein a first plurality of the plurality of reservation loss counters each correspond to a different bad programming reason for reservation loss and a different reservation loss counter not in the first plurality of the plurality of reservation loss counters correspond to a valid programming reason for the reservation loss, the method comprising:
when the reservation loss is due to bad programming, incrementing one of the first plurality of reservation loss counters corresponding to a bad programming reason for the reservation loss; and
when the reservation loss is due to valid programming, incrementing the different reservation loss counter.

17. An integrated circuit processor comprising:
a cache memory that includes a plurality of cache lines, wherein a reservation for a specified memory address comprises a reservation for a cache line that includes the specified memory address;
a performance monitor that logs a plurality of reservation losses in the processor, wherein for a selected one of the plurality of reservation losses, the performance monitor samples less than all addresses that correspond to the selected one reservation loss, and additionally logs a reason for the one selected reservation loss at each sampled address, wherein a reservation loss occurs between a first instruction that gains a reservation on a specified memory address and a second instruction that completes operations on the specified memory address, wherein the first instruction comprises a Load and Reserve Indexed (larx) instruction and the second instruction comprises a Store Conditional Indexed (stcx) instruction defined in an instruction set for a PowerPC processor, wherein the reservation for the cache lin

Assignees

• IBM

Inventors

• Kapoor Shakti
• Schumann John A
• Yokum Karen E

Classifications

• G06F12/0895

  of parts of caches, e.g. directory or tag array · CPC title

• G06F11/3476

  Data logging (G06F11/14, G06F11/2205 take precedence) · CPC title

• G06F11/3024

  where the computing system component is a central processing unit [CPU] · CPC title

• G06F9/3004 Primary

  to perform operations on memory · CPC title

• G06F2212/283

  Plural cache memories · CPC title