Precise verification of a logic problem on a simulation accelerator

Patent metadata

Field	Value
Publication number	US-10896273-B2
Application number	US-201816158468-A
Country	US
Kind code	B2
Filing date	Oct 12, 2018
Priority date	Oct 12, 2018
Publication date	Jan 19, 2021
Grant date	Jan 19, 2021

Abstract

A computer system includes a hardware accelerator and host processor. The hardware accelerator executes a simulation of a first logical model according to a plurality of simulation cycles. The host processor determines a fault checkpoint based on a logic fault that occurs in response to executing the simulation. The host processor verifies removal of the logic fault based on rerunning the simulation from the fault checkpoint.

First claim

What is claimed is:

1. A computer system comprising:
a hardware accelerator configured to execute a simulation of a first logical model according to a plurality of simulation cycles; and
a host processor configured to determine a fault checkpoint based on a logic fault that occurs in response to executing the simulation,
wherein the host processor verifies removal of the logic fault based on rerunning the simulation from the fault checkpoint.

2. The computer system of claim 1 , wherein the host processor determines a preceding cycle among the simulation cycles at which to generate the fault checkpoint based on a faulty cycle among the simulation cycles, the faulty cycle containing the logic fault.

3. The computer system of claim 2 , wherein the host processor includes a logic fault controller that determines the preceding cycle by subtracting a predetermined number of simulation cycles from the faulty cycle.

4. The computer system of claim 2 , wherein the host processor performs a debugging operation to remove the logic fault based on the fault checkpoint.

5. The computer system of claim 4 , wherein the debugging operation includes at least one of a logic fix debugging operation and a mode change debugging operation.

6. The computer system of claim 5 , wherein the logic fix debugging operation includes generating a new logical model and fault checkpoint generated in that new logical model at a simulation cycle that matches the preceding cycle included in the first logical model, and rerunning the simulation of the new logical model starting from the fault checkpoint.

7. The computer system of claim 5 , wherein the mode change debugging operation includes generating the fault checkpoint at the preceding cycle included in the first model, and rerunning the simulation of the first logical model starting from the fault checkpoint according to a changed mode of the accelerator.

8. A method of verifying a logic fault in an accelerator, the method comprising:
executing, via the accelerator, a simulation of a first logical model according to a plurality of simulation cycles;
determining, via a host processor, a fault checkpoint based on a logic fault that occurs in response to executing the simulation; and
verifying, via the host processor, removal of the logic fault based on rerunning the simulation from the fault checkpoint.

9. The method of claim 8 , further comprising determining, via the host processor, a preceding cycle among the simulation cycles at which to generate the fault checkpoint based on a faulty cycle that contains the logic fault.

10. The method of claim 9 , further comprising determining, via a logic fault controller included in the host processor, the preceding cycle by subtracting a predetermined number of simulation cycles from the faulty cycle.

11. The method of claim 9 , further comprising performing a debugging operation to remove the logic fault based on the fault checkpoint.

12. The method of claim 11 , wherein the debugging operation includes at least one of a logic fix debugging operation and a mode change debugging operation.

13. The method of claim 12 , wherein performing the logic fix debugging operation includes:
generating a new logical model and fault checkpoint generated in that new logical model at a simulation cycle that matches the preceding cycle included in the first logical model; and
rerunning the simulation of the new logical model starting from the fault checkpoint.

14. The method of claim 12 , wherein performing the mode change debugging operation includes:
generating the fault checkpoint at the preceding cycle included in the first model; and
rerunning the simulation of the first logical model starting from the fault checkpoint according to a changed mode of the accelerator.

15. A computer program product comprising a computer readable storage medium having program instructions embodied therewith the program instructions executable by a computer processor to cause the computer processor to perform a method of verifying a logic fault in an accelerator, the method comprising:
executing, via the accelerator, a simulation of a first logical model according to a plurality of simulation cycles;
determining, via a host processor, a fault checkpoint based on a logic fault that occurs in response to executing the simulation; and
verifying, via the host processor, removal of the logic fault based on rerunning the simulation from the fault checkpoint.

16. The computer program product of claim 15 , further comprising determining, via the host processor, a preceding cycle among the simulation cycles at which to generate the fault checkpoint based on a faulty cycle that contains the logic fault.

17. The computer program product of claim 16 , further comprising determining, via a logic fault controller included in the host processor, the preceding cycle by subtracting a predetermined number of simulation cycles from the faulty cycle.

18. The computer program product of claim 16 , further comprising performing a debugging operation to remove the logic fault based on the fault checkpoint.

19. The computer program product of claim 18 , wherein performing the debugging operation includes:
generating a new logical model that contains the fault checkpoint at a simulation cycle that matches the preceding cycle included in the first logical model; and
rerunning the simulation of the new logical model starting from the fault checkpoint.

20. The computer program product of claim 18 , wherein performing the debugging operation includes:
generating the fault checkpoint at the preceding cycle included in the first model; and
rerunning the simulation of the first logical model starting from the fault checkpoint according to a changed mode of the accelerator.

Assignees

• IBM

Inventors

• Schumann John A
• Chatterjee Debapriya
• Cockcroft Bryant
• Barnett Kevin
• Hall Piriya K
• Umbarger Paul
• Yokum Karen

Classifications

• G01R31/3177

  Testing of logic operation, e.g. by logic analysers · CPC title

• G01R31/31705

  Debugging aspects, e.g. using test circuits for debugging, using dedicated debugging test circuits (generation of test sequences therefor G01R31/31835, using scan test therefor G01R31/318544) · CPC title

• G06F30/33 Primary

  Design verification, e.g. functional simulation or model checking · CPC title

• G01R31/31704

  Design for test; Design verification (concerning scan tests G01R31/318583; computer-aided design G06F30/00) · CPC title

• G06F30/331 Primary

  with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation · CPC title