Configurable Arithmetic HW Accelerator
US-2024427521-A1 · Dec 26, 2024 · US
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Ryabinin Yuri patents
Ryabinin Yuri is listed as an inventor on 22 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Ryabinin Yuri |
| Total patents | 22 |
| First publication | Mar 2, 2017 |
| Latest publication | Dec 26, 2024 |
Notable patents
Publications ranked by popularity score, then publication date.
Configurable arithmetic HW accelerator
US-12131058-B2 · Oct 29, 2024 · US
Interface bus speed optimization
US-11984192-B2 · May 14, 2024 · US
Interface Bus Speed Optimization
US-2023410858-A1 · Dec 21, 2023 · US
Configurable Arithmetic HW Accelerator
US-2023342070-A1 · Oct 26, 2023 · US
Method and device for simultaneously decoding data in parallel to improve quality of service
US-11487544-B2 · Nov 1, 2022 · US
Decoder for irregular error correcting codes
US-11190219-B1 · Nov 30, 2021 · US
Method and Device for Simultaneously Decoding Data in Parallel to Improve Quality of Service
US-2021216326-A1 · Jul 15, 2021 · US
ECC decoder with selective component disabling based on decoding message resolution
US-10565040-B2 · Feb 18, 2020 · US
Configurable ECC decoder
US-10530393-B2 · Jan 7, 2020 · US
Recent patents
Latest publications not already listed above.
ECC decoder with multiple decoding modes
US-10218384-B2 · Feb 26, 2019 · US
Storage device operations based on bit error rate (BER) estimate
US-10180874-B2 · Jan 15, 2019 · US
Configurable ecc decoder
US-2018159555-A1 · Jun 7, 2018 · US
Ecc decoder with selective component disabling based on decoding message resolution
US-2018157551-A1 · Jun 7, 2018 · US
Ecc decoder with multiple decoding modes
US-2018159556-A1 · Jun 7, 2018 · US
Ecc decoder with multiple decoding modes
US-2018159553-A1 · Jun 7, 2018 · US
Storage module and method for datapath bypass
US-9905314-B2 · Feb 27, 2018 · US
Storage device operations based on bit error rate (BER) estimate
US-9886342-B2 · Feb 6, 2018 · US
Storage device operations based on bit error rate (ber) estimate
US-2017269991-A1 · Sep 21, 2017 · US
On-the-fly syndrome and syndrome weight computation architecture for LDPC decoding
US-9768807-B2 · Sep 19, 2017 · US
Storage device operations based on bit error rate (ber) estimate
US-2017123898-A1 · May 4, 2017 · US
On-the-fly syndrome and syndrome weight computation architecture for ldpc decoding
US-2017063400-A1 · Mar 2, 2017 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Western Digital Tech Inc | 14 |
| Sandisk Technologies Inc | 7 |
| Sandisk Technologies Llc | 5 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| H03M13/1111 | 13 |
| H03M13/1108 | 11 |
| G11C29/52 | 11 |
| G06F3/0679 | 11 |
| H03M13/3707 | 10 |