Interface bus speed optimization

Patent metadata

Field	Value
Publication number	US-11984192-B2
Application number	US-202217841432-A
Country	US
Kind code	B2
Filing date	Jun 15, 2022
Priority date	Jun 15, 2022
Publication date	May 14, 2024
Grant date	May 14, 2024

Abstract

Various devices, such as storage devices or systems are configured to transmit data between various components over one or more interfaces. The operation of these interfaces is based on the mechanical limits of the components doing the communication, often latches. Latches often require a setup and hold time limit on the signal being transmitted to be held a desired value. Because the physical effects of the environment, such as voltage being provided, temperature of the component, for example, can affect the operation of the latch, there is often a large margin used to operate them. These large margins avoid errors but decrease overall speed of the interface. By utilizing a test latch within an interface bus group with a drop in operating voltage, changes in output detected can be indicative of upcoming errors. Once detected, the error can be remedied by increasing voltage, lowering operating speeds, or cooling the components.

First claim

What is claimed is:

1. A device comprising a plurality of components, including:
a processor;
a memory array comprising a plurality of memory devices;
an interface bus comprising at least a plurality of latches configured to receive and output data and a clock signal;
a power supply configured to provide power to the plurality of latches wherein the power supplied to at least one of the plurality of latches is configured to provide a different voltage; and
an interface bus optimization logic configured to:
direct the power supply to provide power to the plurality of latches;
direct the output of at least two of the plurality of latches into a comparator wherein a first latch is provided a first voltage and a second latch is provided the different second voltage;
monitor the comparator output to determine the presence of an error in at least one of the latches; and
execute, in response to a determined error, a remedial action associated with the plurality of latches.

2. The device of claim 1 , wherein the different voltage is a voltage drop.

3. The device of claim 2 , wherein the voltage drop is achieved through the use of a resistor between the power supply and the at least one of the plurality of latches.

4. The device of claim 2 , wherein the voltage drop is static and determined at the time of manufacture.

5. The device of claim 2 , wherein the voltage drop is configured to be dynamically changed by the interface bus optimization logic.

6. The device of claim 5 , wherein the voltage drop is achieved through the use of a variable resistor.

7. The device of claim 5 , wherein the plurality of latches are configured for use in an interface and the voltage drop is changed based on the type of interface.

8. The device of claim 5 , wherein the plurality of latches are configured for use in an interface and the voltage drop is changed based on the type of data being transmitted across the interface.

9. The device of claim 1 , wherein the comparator is an exclusive-OR (XOR) gate.

10. The device of claim 1 , wherein the first latch and second latch are located within the same thermal zone.

11. The device of claim 1 , wherein the plurality of latches is configured into a bus group for an interface.

12. The device of claim 11 , wherein the latch provided a second different voltage is also configured into the bus group.

13. The device of claim 1 , wherein the second latch is the same model of component as the first latch.

14. The device of claim 1 , wherein the remedial action is to increase the voltage of the power provided by the power supply.

15. The device of claim 1 , wherein the remedial action is to decrease the clock signal frequency.

16. The device of claim 1 , wherein the remedial action is to direct one or more cooling actions configured to decrease the temperature of the plurality of latches.

17. A method, comprising:
directing a power supply of a storage device to provide power to a plurality of latches configured in a bus group for an interface wherein a first latch is provided a first voltage and a second latch is provided a lower second voltage;
directing the output of first latch and second latch into a comparator;
monitoring the comparator output to determine the presence of an error in at least one of the latches;
determining if a first remedial action associated with the plurality of latches can be performed; and
performing, in response to determining the action can be performed, the remedial action.

18. The method of claim 17 , wherein the first remedial action is to direct the power supply to increase the voltage provided.

19. The method of claim 18 , wherein, in the event the voltage cannot be increased:
determining if the clock signal frequency associated with the plurality of latches can be decreased; and
decreasing the clock signal frequency, in response to determining the clock signal frequency can be decreased.

20. A device, including:
a processor;
an interface bus comprising at least a plurality of components configured to receive and output data;
a power supply configured to provide power to the plurality of components at a first voltage wherein the power supplied to at least one of the components is configured to provide a second lower voltage; and
an interface bus optimization logic configured to:
direct the data output of at least two of the components into a comparator;
monitor the comparator output to determine the presence of a different of output between the at least two components; and
execute, in response to a determined error, a remedial action configured to correct the difference in component output.

Assignees

• Western Digital Tech Inc

Inventors

• Zehavi Mordekhay
• Asfur Mahmud
• Tamir Yossef
• Ryabinin Yuri

Classifications

• G11C7/1048 Primary

  Data bus control circuits, e.g. precharging, presetting, equalising · CPC title

• G11C5/14

  Power supply arrangements {, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels} · CPC title

• G11C7/1039

  using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers · CPC title

• G11C7/22

  Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management · CPC title

• G11C29/52

  Protection of memory contents; Detection of errors in memory contents · CPC title