Ecc decoder with multiple decoding modes

Patent metadata

Field	Value
Publication number	US-2018159553-A1
Application number	US-201615366859-A
Country	US
Kind code	A1
Filing date	Dec 1, 2016
Priority date	Dec 1, 2016
Publication date	Jun 7, 2018
Grant date	—

Abstract

A device includes a low density parity check (LDPC) decoder that configured to receive a representation of a codeword. The LDPC decoder includes a message memory configured to store decoding messages, multiple data processing units (DPUs), a control circuit, and a reording circuit. The control circuit is configured to enable a first number of the DPUs to decode the representation of the codeword in response to a decoding mode indicator indicating a first decoding mode and to enable a second number of the DPUs to decode the representation of the codeword in response to the decoding mode indicator indicating a second decoding mode. The reordering circuit is configured to selectively reorder at least one of the decoding messages based on the decoding mode indicator.

First claim

1 . A device comprising:
a non-volatile memory; and a low density parity check (LDPC) decoder configured to receive a representation of a codeword read from to the non-volatile memory, the LDPC decoder comprising:
a message memory configured to store decoding messages;
multiple data processing units (DPUs);
a control circuit responsive to a decoding mode indicator, the control circuit configured to enable a first number of the DPUs to decode the representation of the codeword in response to the decoding mode indicator indicating a first decoding mode and to enable a second number of the DPUs to decode the representation of the codeword in response to the decoding mode indicator indicating a second decoding mode; and
a reordering circuit coupled to the control circuit and configured to selectively reorder at least one of the decoding messages based on the decoding mode indicator.

2 . The device of claim 1 , wherein the LDPC decoder is configured to process the representation of the codeword based on a quasi-cyclic LDPC (QC-LDPC) parity check matrix that has a first block matrix size, and wherein the reordering circuit is configured to selectively reorder the decoding messages to transform the QC-LDPC parity check matrix to a second QC-LDPC parity check matrix having a second block matrix size.

3 . The device of claim 2 , wherein the reordering circuit is further configured to selectively reorder the decoding messages to transform the QC-LDPC parity check matrix to a third QC-LDPC parity check matrix having a third block matrix size.

4 . The device of claim 1 , wherein the first decoding mode uses first decoding messages having a first size, the second decoding mode uses second decoding messages having a second size that is larger than the first size, and the first number of DPUs is greater than the second number of DPUs.

5 . The device of claim 4 , wherein each iteration of a first decoding operation of the first decoding mode uses the first decoding messages to generate first modified decoding messages, wherein each of the first decoding messages resides in consecutive memory addresses, and wherein each of the first modified decoding messages is written into consecutive memory addresses.

6 . The device of claim 4 , wherein each iteration of a second decoding operation of the second decoding mode uses the second decoding messages to generate second modified decoding messages, wherein each of the second decoding messages resides in consecutive memory addresses, and wherein each of the second modified decoding messages is written into consecutive memory addresses.

7 . The device of claim 4 , further comprising a decoder clock, wherein a first frequency of the decoder clock in the first decoding mode is substantially the same as a second frequency of the decoder clock in the second decoding mode, and wherein a first power consumption of the LDPC decoder per cycle of the decoder clock in the first decoding mode is substantially the same as a second power consumption of the LDPC decoder per cycle of the decoder clock in the second decoding mode.

8 . The device of claim 1 , wherein the message memory includes:
a variable node memory configured to store decoding messages corresponding to variable node values; and a check node memory configured to store decoding messages corresponding to check node values, and wherein the LDPC decoder further comprises: an output buffer coupled to the variable node memory; a first data processing unit (DPU) module including a first group of DPUs corresponding to the first decoding mode; a second DPU module including a second group of DPUs corresponding to the second decoding mode; and a third DPU module including a third group of DPUs corresponding to a third decoding mode.

9 . The device of claim 1 , wherein numbers of active DPUs in each particular decoding mode are set to be are inversely proportional to average power consumption of the active DPUs in the particular decoding mode, proportional to a frequency of use of the particular decoding mode, inversely proportional to message resolution of the active DPUs in the particular decoding mode, or any combination thereof.

10 . The device of claim 1 , wherein in the first decoding mode the reordering circuit generates a first permuted version of the representation of the codeword, and in the second decoding mode the reordering circuit generates a second permuted version of the representation of the codeword.

11 . The device of claim 1 , wherein in the first decoding mode the LDPC decoder is configured to process the representation of the codeword based on a first permuted version of a quasi-cyclic LDPC (QC-LDPC) parity check matrix and wherein in the second decoding mode the LDPC decoder is configured to process the representation of the codeword based on a second permuted version of the QC-LDPC parity check matrix.

12 . The device of claim 1 , wherein in the first decoding mode the LDPC decoder is configured to process the representation of the codeword based on a first quasi-cyclic LDPC (QC-LDPC) parity check matrix and wherein in the second decoding mode the LDPC decoder is configured to process the representation of the codeword based on a second QC-LDPC parity check matrix.

13 . A method comprising:
at a device including a non-volatile memory and a low density parity check (LDPC) decoder, the LDPC decoder including multiple data processing units (DPUs), a control circuit, a reordering circuit, and a message memory configured to store decoding messages, performing:
receiving, at the LDPC decoder, a representation of a codeword read from the non-volatile memory,
enabling a number of the DPUs to decode the representation of the codeword responsive to a decoding mode indicator, wherein a first number of the DPUs correspond to a first decoding mode and a second number of the DPUs correspond to a second decoding mode; and
selectively reordering at least one of the decoding messages based on the decoding mode indicator.

14 . The method of claim 13 , wherein reordering the at least one decoding message corresponds to transforming a quasi-cyclic LDPC (QC-LDPC) parity check matrix having a first block matrix size to a second QC-LDPC parity check matrix having a second block matrix size.

15 . The method of claim 13 , wherein the first decoding mode uses first decoding messages having a first size, the second decoding mode uses second decoding messages having a second size that is larger than the first size, and the first number of DPUs is greater than the second number of DPUs.

16 . The method of claim 15 , wherein the first decoding mode corresponds to a bit-flipping configuration, the first size is one bit, and the second decoding mode corresponds to an iterative message-passing decoding configuration.

17 . The method of claim 15 , wherein the first decoding mode corresponds to a first iterative message-passing decoding configuration, the second decoding mode corresponds to a second iterative message-passing decoding configuration, the first number is twice the second number, and the second size is twice the first size.

18 . An apparatus comprising:
means for storing a representation of a codeword; and means for low-density parity check (LDPC) decoding the representation of the codeword, the means for LDPC decoding comprising:
means for storing decoding messages;
multiple means for processing data;
means for enabling a first number of the means for processing data to decode the representation of the codeword in response to a decoding mode indicator ind

Assignees

• Sandisk Technologies Llc

Inventors

• Sharon Eran
• Goldenberg Idan
• Ilani Ishai
• Alrod Idan
• Ryabinin Yuri
• Dumchin Yan
• Fiterman Mark
• Zamir Ran

Classifications

• G06F3/064

  Management of blocks · CPC title

• H03M13/3707

  Adaptive decoding and hybrid decoding, e.g. decoding methods or techniques providing more than one decoding algorithm for one code · CPC title

• H03M13/1111 Primary

  Soft-decision decoding, e.g. by means of message passing or belief propagation algorithms · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F11/1076

  Parity data used in redundant arrays of independent storages, e.g. in RAID systems · CPC title