Configurable Arithmetic HW Accelerator

Patent metadata

Field	Value
Publication number	US-2023342070-A1
Application number	US-202217726755-A
Country	US
Kind code	A1
Filing date	Apr 22, 2022
Priority date	Apr 22, 2022
Publication date	Oct 26, 2023
Grant date	—

Abstract

A data storage device includes a memory device and a controller coupled to the memory device. The controller includes a decoder multiplexer (mux) module, a plurality of request/response channels coupled to the decoder mux module, an arithmetic pipeline module coupled to the plurality of request/response channels, an arbiter module coupled to the plurality of request/response channels and the arithmetic pipeline module, a mux/arbiter module coupled to the arithmetic pipeline module, a random access memory (RAM) access module coupled to the decoder mux module and the mux/arbiter module, and a RAM coupled to the mux/arbiter module. The controller is configured to determine a pipeline depth value and a calculation parallelism value of the arithmetic pipeline module and configure the arithmetic pipeline module based on the determining.

First claim

What is claimed is:

1 . A data storage device, comprising:
a memory device; and a controller coupled to the memory device, wherein the controller comprises:
a decoder multiplexer (mux) module;
a plurality of request/response channels coupled to the decoder mux module;
an arithmetic pipeline module coupled to the plurality of request/response channels;
an arbiter module coupled to the plurality of request/response channels and the arithmetic pipeline module;
a mux/arbiter module coupled to the arithmetic pipeline module;
a random access memory (RAM) access module coupled to the decoder mux module and the mux/arbiter module; and
a RAM coupled to the mux/arbiter module.

2 . The data storage device of claim 1 , wherein the controller is configured to store static parameters and deliver the static parameters to the arithmetic pipeline module, wherein the arithmetic pipeline module is disposed in a calculation accelerator module of the controller.

3 . The data storage device of claim 1 , wherein the controller is configured to determine a calculation configuration based on a received input and provide the calculation configuration to the arithmetic pipeline module of a calculation module of the controller.

4 . The data storage device of claim 3 , wherein one or more static parameters are provided to the arithmetic pipeline module based on the calculation configuration.

5 . The data storage device of claim 3 , wherein the calculation configuration comprises one or more definitions to set a structure of the arithmetic pipeline module and set an order of calculations of the arithmetic pipeline module.

6 . The data storage device of claim 5 , wherein the structure of the arithmetic pipeline module is configurable based on calculation parallelism value and pipeline depth value, wherein the structure comprises a plurality of stages, and wherein a number of the plurality of stages is configurable based on the calculation parallelism value and the pipeline depth value.

7 . The data storage device of claim 6 , wherein the controller is configured to, for each stage of the plurality of stages, perform a plurality of arithmetic calculations based on the order of calculations.

8 . The data storage device of claim 7 , wherein results of the plurality of arithmetic calculations are provided to a next stage of the plurality of stages, and wherein last results of the plurality of arithmetic calculations are sent to the plurality of request/response channels.

9 . The data storage device of claim 1 , wherein the controller is configured to use the plurality of request/response channels to activate the arithmetic pipeline module and to receive calculation results from the arithmetic pipeline module.

10 . The data storage device of claim 1 , wherein the controller further comprises a plurality of central processing units (CPUs), and wherein each CPU is associated with a request/response channel of the plurality of request/response channels.

11 . The data storage device of claim 1 , wherein the arbiter module is configured to:
arbitrate between the plurality of request/response channels when a threshold number of outstanding requests of the arithmetic pipeline module is exceeded; and provide an outstanding request to the arithmetic pipeline module based on the arbitrating.

12 . The data storage device of claim 1 , wherein the controller is configured to store configurations/databases that are greater than a threshold size in the RAM.

13 . A data storage device, comprising:
a memory device; and a controller coupled to the memory device, wherein the controller comprises an arithmetic pipeline module, and wherein the controller is configured to:
determine a pipeline depth value and a calculation parallelism value of the arithmetic pipeline module, wherein the pipeline depth value is a number of stages to perform a series of calculations and the calculation parallelism value is a number of parallel arithmetic elements of each calculation of the series of calculations, wherein each calculation of the series of calculations comprises a plurality of distinct arithmetic elements; and
configure the arithmetic pipeline module based on the determining.

14 . The data storage device of claim 13 , wherein the arithmetic pipeline module comprises a pipeline control module coupled to the arithmetic pipeline module, and wherein the pipeline control module is configured to:
control an operation of the arithmetic pipeline module according to values of one or more registers located in a calculation configuration storage location of the controller.

15 . The data storage device of claim 14 , wherein the values are used to determine the pipeline depth value and the calculation parallelism value.

16 . The data storage device of claim 13 , wherein the plurality of distinct arithmetic elements further includes an arithmetic element having a configurable, algorithm-specific calculation.

17 . The data storage device of claim 13 , wherein the pipeline depth value is a first value and the calculation parallelism value is a second value, and wherein the first value and the second value are configured based on a tradeoff between latency, timing, area, and power per application.

18 . A data storage device, comprising:
memory means; and a controller coupled to the memory means, wherein the controller comprises:
a plurality of multiplexers;
a plurality of arithmetic elements; and
a plurality of registers and/or a plurality of flip-flops; and wherein the controller is configured to:
determine a pipeline depth value and a calculation parallelism value; and
configure an arithmetic pipeline module based on the pipeline depth value and the calculation parallelism value, wherein configuring comprises selecting and deselecting one or more multiplexers of the plurality of multiplexers, one or more arithmetic elements of the plurality of arithmetic elements, and one or more registers of the plurality of registers and/or one or more flip-flops of the plurality of flip-flops.

19 . The data storage device of claim 18 , wherein the plurality of arithmetic elements is selected from a group consisting of dividers, multipliers, adders, subtractors, comparators, shifters, multiplexers, and combinations thereof.

20 . The data storage device of claim 19 , wherein the plurality of arithmetic elements is predetermined.

Assignees

• Western Digital Tech Inc

Inventors

• Ryabinin Yuri
• Benisty Shay

Classifications

• G06F3/0655 Primary

  Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices · CPC title

• G06F3/0604

  Improving or facilitating administration, e.g. storage management · CPC title

• G06F3/0679 Primary

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F3/061

  Improving I/O performance · CPC title