Configurable ecc decoder

Patent metadata

Field	Value
Publication number	US-2018159555-A1
Application number	US-201715638045-A
Country	US
Kind code	A1
Filing date	Jun 29, 2017
Priority date	Dec 1, 2016
Publication date	Jun 7, 2018
Grant date	—

Abstract

A device includes a low density parity check (LDPC) decoder that is configured to receive a representation of a codeword. The LDPC decoder includes a circuit configured to set a message length of a decoding message at least partially based on an error metric associated with the representation of the codeword. The LDPC decoder also includes a processing unit including a first group of components and a second group of components. The processing unit configured to selectively couple the first group of components to the second group of components based on the message length of the decoding message.

First claim

What is claimed is:

1 . A method comprising:
at a device including a non-volatile memory and a low density parity check (LDPC) decoder, performing:
receiving, at the LDPC decoder, a representation of a codeword from the non-volatile memory;
setting a message length of a decoding message at least partially based on an error metric associated with the representation of the codeword; and
selectively coupling a first group of components of the LDPC decoder to a second group of components of the LDPC decoder based on the message length.

2 . The method of claim 1 , wherein setting the message length at least partially based on the error metric includes setting the decoding message to have a first number of bits in response to the error metric exceeding a threshold.

3 . The method of claim 1 , wherein the error metric comprises a syndrome weight of the representation of the codeword.

4 . The method of claim 1 , wherein:
the first group of components includes a first group of serially-coupled adders; and the second group of components includes a second group of serially-coupled adders.

5 . The method of claim 4 , wherein selectively coupling the first group of components to the second group of components includes sending a control signal to a control input of a switch that is coupled to an output of the first group of serially-coupled adders and that is coupled to an input of the second group of serially-coupled adders.

6 . The method of claim 1 , wherein:
the first group of components includes a first portion of a memory of the LDPC decoder, and the second group of components includes a second portion of the memory.

7 . The method of claim 6 , further comprising storing a first message having a first length in the first portion and the second portion.

8 . The method of claim 6 , further comprising storing a second message in the first portion and a third message in the second portion.

9 . A device comprising:
a non-volatile memory; and a low density parity check (LDPC) decoder configured to receive a representation of a codeword from the non-volatile memory, the LDPC decoder comprising:
a circuit configured to set a message length of a decoding message at least partially based on an error metric associated with the representation of the codeword; and
a processing unit including a first group of components and a second group of components, the processing unit configured to selectively couple the first group of components to the second group of components based on the message length of the decoding message.

10 . The device of claim 9 , wherein:
the LDPC decoder further comprises a memory that includes a first portion and a second portion; the memory is configured to couple the first portion to the second portion to store a first message having a first length; and the memory is configured to decouple the first portion from the second portion to store a second message in the first portion and to store a third message in the second portion.

11 . The device of claim 10 , wherein the second message and the third message each have a second length that is less than the first length.

12 . The device of claim 9 , wherein:
the first group of components includes first serially-coupled adding units; the second group of components includes second serially-coupled adding units; and the processing unit further includes a switch coupled to an output of the first group and to an input of the second group, the switch configured to:
couple the output of the first group to the input of the second group in response to a first control signal that indicates a first message length; and
decouple the output of the first group from the input of the second group in response to a second control signal that indicates a second message length, the second message length less than the first message length.

13 . The device of claim 12 , wherein:
the processing unit is configured, while the output of the first group is coupled to the input of the second group, to add a first message to a second message, wherein each of the first message and the second message has the first message length; and the processing unit is configured, while the output of the first group is decoupled from the input of the second group, to:
add a third message to a fourth message at the first serially-coupled adding units; and
add a fifth message to a sixth message at the second serially-coupled adding units,
wherein each of the third message, the fourth message, the fifth message, and the sixth message has the second message length.

14 . The device of claim 13 , wherein:
the message length is set to the first message length in a first decoding mode of the LDPC decoder; and the message length is set to the second message length in a second decoding mode of the LDPC decoder.

15 . The device of claim 14 , wherein:
the LDPC decoder further comprises a decoder clock; the processing unit is configured to process one pair of messages per clock cycle of the decoding clock in each pipeline stage in the first decoding mode; and the processing unit is configured to process multiple pairs of messages in parallel per clock cycle of the decoding clock in each pipeline stage in the second decoding mode.

16 . The device of claim 9 , wherein each of the first group of components and the second group of components includes at least one of: flip-flops, subtractors, multiplexers, or comparators.

17 . The device of claim 9 , wherein the circuit is further configured to selectively set a reduced-power configuration of one or more components of the LDPC decoder at least partially based on a decoding mode indicator and an error metric associated with the codeword, the reduced-power configuration including at least one of:
a reduced number of data processing units (DPUs) that are enabled; a reduced clock frequency of a decoder clock; or a reduced supply voltage of the LDPC decoder.

18 . An apparatus comprising:
means for storing data; and means for low density parity check (LDPC) decoding a representation of a codeword from the means for storing data, the means for LDPC decoding comprising:
means for setting a message length of a decoding message at least partially based on an error metric associated with the representation of the codeword; and
means for selectively coupling a first group of components to a second group of components based on the message length.

19 . The apparatus of claim 18 , wherein the means for selectively coupling is further configured to:
couple an output of a first means for adding to an input of a second means for adding in response to a first control signal that indicates a first length; and decouple the output of the first means for adding from the input of the second means for adding in response to a second control signal that indicates a second length, the second length less than the first length.

20 . The apparatus of claim 19 , wherein the means for setting the message length is further configured to generate the first control signal and the second control signal.

Assignees

• Western Digital Tech Inc

Inventors

• Ryabinin Yuri
• Dumchin Yan

Classifications

• H03M13/616

  Matrix operations, especially for generator matrices or check matrices, e.g. column or row permutations · CPC title

• H03M13/1137

  Partly parallel processing, i.e. sub-blocks or sub-groups of nodes being processed in parallel · CPC title

• H03M13/6577

  Representation or format of variables, register sizes or word-lengths and quantization · CPC title

• H03M13/3715

  Adaptation to the number of estimated errors or to the channel state · CPC title

• H03M13/6511

  Support of multiple decoding rules, e.g. combined MAP and Viterbi decoding · CPC title