Configurable ECC decoder

Patent metadata

Field	Value
Publication number	US-10530393-B2
Application number	US-201715638045-A
Country	US
Kind code	B2
Filing date	Jun 29, 2017
Priority date	Dec 1, 2016
Publication date	Jan 7, 2020
Grant date	Jan 7, 2020

Abstract

A device includes a low density parity check (LDPC) decoder that is configured to receive a representation of a codeword. The LDPC decoder includes a circuit configured to set a message length of a decoding message at least partially based on an error metric associated with the representation of the codeword. The LDPC decoder also includes a processing unit including a first group of components and a second group of components. The processing unit configured to selectively couple the first group of components to the second group of components based on the message length of the decoding message.

First claim

What is claimed is:

1. A method comprising:
at a device including a non-volatile memory and a low density parity check (LDPC) decoder, performing:
receiving, at the LDPC decoder, a codeword from the non-volatile memory;
setting a message length of decoding messages at least partially based on a syndrome weight of the codeword;
selectively coupling a first group of serially-coupled adders of the LDPC decoder to a second group of serially-coupled adders of the LDPC decoder based on the message length;
adding multiple pairs of the decoding messages in parallel per clock cycle of a decoding clock with the first group of serially-coupled adders and the second group of serially-coupled adders when the first group of serially-coupled adders is not coupled to the second group of serially-coupled adders; and
adding a single pair of the decoding messages per clock cycle of the decoding clock with the first group of serially-coupled adders and the second group of serially-coupled adders when the first group of serially-coupled adders is coupled to the second group of serially-coupled adders.

2. The method of claim 1 , wherein setting the message length at least partially based on the syndrome weight of the codeword includes setting the decoding messages to have a first number of bits in response to the syndrome weight of the codeword exceeding a threshold.

3. The method of claim 1 , wherein selectively coupling the first group of serially-coupled adders to the second group of serially-coupled adders includes sending a control signal to a control input of a switch that is coupled to an output of the first group of serially-coupled adders and that is coupled to an input of the second group of serially-coupled adders.

4. The method of claim 1 , further comprising selectively coupling a first portion of a memory of the LDPC decoder to a second portion of the memory based on the message length.

5. The method of claim 4 , further comprising storing a first message having a first length in the first portion and the second portion.

6. The method of claim 4 , further comprising storing a second message in the first portion and a third message in the second portion.

7. A device comprising:
a non-volatile memory; and
a low density parity check (LDPC) decoder configured to receive a representation of a codeword from the non-volatile memory, the LDPC decoder comprising:
a decoding clock;
a circuit configured to set a message length of decoding messages at least partially based on a syndrome weight of the codeword; and
a processing unit including first serially-coupled adding units and second serially-coupled adding units, the processing unit configured to
selectively couple the first serially-coupled adding units to the second serially-coupled adding units based on the message length of the decoding messages,
add multiple pairs of the decoding messages in parallel per clock cycle of the decoding clock with the first serially-coupled adding units and the second serially-coupled adding units when the first serially-coupled adding units are not coupled to the second serially-coupled adding units, and
add a single pair of the decoding messages per clock cycle of the decoding clock with the first serially-coupled adding units and the second serially-coupled adding units when the first serially-coupled adding units are coupled to the second serially-coupled adding units.

8. The device of claim 7 , wherein:
the LDPC decoder further comprises a memory that includes a first portion and a second portion;
the memory is configured to couple the first portion to the second portion to store a first message having a first length; and
the memory is configured to decouple the first portion from the second portion to store a second message in the first portion and to store a third message in the second portion.

9. The device of claim 8 , wherein the second message and the third message each have a second length that is less than the first length.

10. The device of claim 7 , wherein:
the processing unit further includes a switch coupled to an output of the first serially-coupled adding units and to an input of the second serially-coupled adding units, the switch configured to:
couple the output of the first serially-coupled adding units to the input of the second serially-coupled adding units in response to a first control signal that indicates a first message length; and
decouple the output of the first serially-coupled adding units from the input of the second serially-coupled adding units in response to a second control signal that indicates a second message length, the second message length less than the first message length.

11. The device of claim 10 , wherein:
the processing unit is configured, while the output of the first serially-coupled adding units is coupled to the input of the second serially-coupled adding units, to add a first message to a second message, wherein each of the first message and the second message has the first message length; and
the processing unit is configured, while the output of the first serially-coupled adding units is decoupled from the input of the second serially-coupled adding units, to:
add a third message to a fourth message at the first serially-coupled adding units; and
add a fifth message to a sixth message at the second serially-coupled adding units,
wherein each of the third message, the fourth message, the fifth message, and the sixth message has the second message length.

12. The device of claim 11 , wherein:
the message length is set to the first message length in a first decoding mode of the LDPC decoder; and
the message length is set to the second message length in a second decoding mode of the LDPC decoder.

13. The device of claim 7 , wherein the circuit is further configured to selectively set a reduced-power configuration of one or more components of the LDPC decoder at least partially based on a decoding mode indicator and that syndrome weight of the codeword, the reduced-power configuration including at least one of:
a reduced number of data processing units (DPUs) that are enabled;
a reduced clock frequency of the decoder clock; or
a reduced supply voltage of the LDPC decoder.

14. An apparatus comprising:
means for storing data; and
means for low density parity check (LDPC) decoding a representation of a codeword from the means for storing data, the means for LDPC decoding comprising:
means for setting a message length of decoding messages at least partially based on a syndrome weight of the codeword; and
means for selectively coupling a first means for adding to a second means for adding based on the message length;
means for adding multiple pairs of the decoding messages in parallel per clock cycle of a decoding clock with the first means for adding and the second means for adding when the first means for adding are not coupled to the second means for adding; and
means for adding a single pair of the decoding messages per clock cycle of the decoding clock with the first means for adding and the second means for adding when the first means for adding are coupled to the second means for adding.

15. The apparatus of claim 14 , wherein the means for selectively coupling is further configured to:
couple an output of the first means for adding to an input of the second means for adding in response to a first control signal that indicates a first length; and
decouple the output of the first means for adding from the input of the second means for adding in response to a second control signal that indicates a second length, the second length less than

Assignees

• Western Digital Tech Inc

Inventors

• Ryabinin Yuri
• Dumchin Yan

Classifications

• H03M13/6586

  Modulo/modular normalization, e.g. 2's complement modulo implementations · CPC title

• H03M13/6577

  Representation or format of variables, register sizes or word-lengths and quantization · CPC title

• H03M13/6511

  Support of multiple decoding rules, e.g. combined MAP and Viterbi decoding · CPC title

• H03M13/1108 Primary

  Hard decision decoding, e.g. bit flipping, modified or weighted bit flipping · CPC title

• H03M13/3715

  Adaptation to the number of estimated errors or to the channel state · CPC title