Ecc decoder with selective component disabling based on decoding message resolution

Patent metadata

Field	Value
Publication number	US-2018157551-A1
Application number	US-201715630906-A
Country	US
Kind code	A1
Filing date	Jun 22, 2017
Priority date	Dec 1, 2016
Publication date	Jun 7, 2018
Grant date	—

Abstract

A device includes a non-volatile memory and a low density parity check (LDPC) decoder configured to receive a representation of a codeword from the non-volatile memory. The LDPC decoder includes multiple data processing units (DPUs) and a control circuit coupled to the DPUs. The control circuit is responsive to an error metric associated with the representation of the codeword and is configured to set a message resolution at least partially based on the error metric and to selectively disable one or more components of the LDPC decoder based on the message resolution.

First claim

What is claimed is:

1 . A device comprising:
a non-volatile memory; and a low density parity check (LDPC) decoder configured to receive a representation of a codeword from the non-volatile memory, the LDPC decoder comprising:
multiple data processing units (DPUs); and
a control circuit coupled to the DPUs and responsive to an error metric associated with the representation of the codeword, the control circuit configured to:
set a message resolution at least partially based on the error metric; and
selectively disable one or more components of the LDPC decoder based on the message resolution.

2 . The device of claim 1 , the LDPC decoder further comprising a memory that has multiple portions, the memory configured to distribute message bits across the multiple portions, and wherein the control circuit is further configured to disable a portion of the message memory that corresponds to an unused message bit.

3 . The device of claim 1 , the LDPC decoder further comprising an adding circuit configured to add multiple messages together, the control circuit further configured to disable operation of a portion of the adding circuit corresponding to an unused message bit.

4 . The device of claim 3 , wherein the control circuit is further configured to set a value of the unused message bit to prevent toggling of the portion of the message adding circuit.

5 . The device of claim 1 , the LDPC decoder further comprising a shifter circuit, the control circuit further configured to disable a portion of the shifter circuit.

6 . The device of claim 1 , the LDPC decoder further comprising a pipeline register, the control circuit further configured to disable a portion of the pipeline register based on the message resolution.

7 . The device of claim 1 , the control circuit further configured to determine the message resolution as a function of the error metric.

8 . The device of claim 1 , the control circuit further configured to adjust the message resolution on-the-fly during decoding.

9 . The device of claim 1 , wherein the error metric is a syndrome weight.

10 . The device of claim 1 , wherein:
the decoder further comprises a decoder clock; the control circuit is further responsive to a decoding mode indicator, the control circuit is further configured to selectively set a reduced-power configuration of one or more components of the LDPC decoder at least partially based on the decoding mode indicator and the error metric; and the reduced-power configuration includes at least one of:
a reduced number of the data processing units (DPUs) that are enabled;
a reduced clock frequency of the decoder clock; or
a reduced supply voltage of the LDPC decoder.

11 . A method comprising:
at a device including a non-volatile memory and a low density parity check (LDPC) decoder, performing:
receiving, at the LDPC decoder, a representation of a codeword from the non-volatile memory;
setting a message resolution at least partially based on an error metric associated with the representation of the codeword; and
selectively disabling one or more components of the LDPC decoder based on the message resolution.

12 . The method of claim 11 , wherein the message resolution is set to a first resolution corresponding to a first number of bits in response to the error metric exceeding a threshold and is set to a second resolution corresponding to a second number of bits in response to the error metric not exceeding the threshold.

13 . The method of claim 12 , wherein a particular component of the one or more components is enabled in response to the message resolution being set to the first resolution and is disabled in response to the message resolution being set to the second resolution.

14 . The method of claim 11 , wherein selectively disabling the one or more components includes disabling a portion of a memory of the LDPC decoder, the portion corresponding to an unused message bit.

15 . The method of claim 11 , wherein selectively disabling the one or more components includes disabling operation of a portion of a message adding circuit of the LDPC decoder, the portion of the message adding circuit corresponding to an unused message bit.

16 . The method of claim 11 , wherein selectively disabling the one or more components includes disabling a portion of a shifter circuit of the LDPC decoder.

17 . The method of claim 11 , wherein selectively disabling the one or more components includes disabling a portion of a pipeline register of the LDPC decoder based on the message resolution.

18 . The method of claim 11 , further comprising adjusting the message resolution on-the-fly during decoding.

19 . An apparatus comprising:
means for storing data; and means for low density parity check (LDPC) decoding of a representation of a codeword from the means for storing data, the means for LDPC decoding comprising:
means for setting a message resolution at least partially based on an error metric corresponding to the representation of the codeword and for selectively disabling one or more components of the means for LDPC decoding based on the message resolution.

20 . The apparatus of claim 19 , the means for LDPC decoding further comprising a means for storing a message as message bits distributed across multiple storage portions, and wherein the means for setting and selectively disabling is further configured to disable a storage portion that corresponds to an unused message bit.

Assignees

• Western Digital Tech Inc

Inventors

• Ryabinin Yuri
• Dumchin Yan

Classifications

• G11C29/52

  Protection of memory contents; Detection of errors in memory contents · CPC title

• H03M13/1111

  Soft-decision decoding, e.g. by means of message passing or belief propagation algorithms · CPC title

• H03M13/6577

  Representation or format of variables, register sizes or word-lengths and quantization · CPC title

• H03M13/6511

  Support of multiple decoding rules, e.g. combined MAP and Viterbi decoding · CPC title

• G06F1/32

  Means for saving power · CPC title