Decoder for irregular error correcting codes

Patent metadata

Field	Value
Publication number	US-11190219-B1
Application number	US-202016917870-A
Country	US
Kind code	B1
Filing date	Jun 30, 2020
Priority date	Jun 30, 2020
Publication date	Nov 30, 2021
Grant date	Nov 30, 2021

Abstract

An error correcting code (ECC) decoder for a non-volatile memory device is configured to decode data stored by the non-volatile memory device using a parity check matrix with columns of different column weights. The ECC decoder is further configured to artificially slow processing of one or more of the columns of the parity check matrix in response to column weights for the one or more columns satisfying a threshold.

First claim

What is claimed is:

1. An apparatus comprising:
a non-volatile memory device; and
an error correcting code (ECC) decoder for the non-volatile memory device, the ECC decoder configured to:
decode data stored by the non-volatile memory device using a parity check matrix with columns of different column weights, and
process a first set of the columns of the parity check matrix at a first speed in response to column weights for the first set of columns failing to satisfy a threshold, and
artificially slow processing of a second set of the columns of the parity check matrix to a slower speed than the first speed in response to column weights for the second set of columns satisfying the threshold.

2. The apparatus of claim 1 , wherein the ECC decoder is configured to artificially slow processing of the second set of columns by using only a subset of available processing units to process the second set of columns such that one or more other processing units are idle.

3. The apparatus of claim 1 , wherein the ECC decoder is configured to artificially slow processing of the second set of columns by reducing a number of messages calculated per bit per clock cycle for the second set of columns when compared to a number of messages calculated per bit per clock cycle for the first set of columns.

4. The apparatus of claim 1 , further comprising an ECC encoder for the non-volatile memory device, the ECC encoder configured to encode the data stored by the non-volatile memory device by enforcing a maximum number of edges in a window of clock cycles such that the ECC decoder artificially slows the processing of the second set of columns of the parity check matrix in response to the column weights satisfying the threshold.

5. The apparatus of claim 1 , wherein the ECC decoder is configured to artificially slow processing of the second set of columns by waiting a number of clock cycles without processing one of the columns in response to the second set of columns satisfying the threshold.

6. The apparatus of claim 5 , wherein the number of clock cycles is selected based on the column weights for the second set of columns.

7. The apparatus of claim 1 , wherein the ECC decoder is configured to artificially slow processing of the second set of columns by rescheduling processing of the second set of columns such that the ECC decoder is configured to process one or more columns of the first set of columns between the processing of the columns of the second set.

8. The apparatus of claim 1 , wherein the ECC decoder is configured to temporally distribute processing of the second set of columns among processing units such that one or more columns of the first set of columns are processed by processing units disposed between processing units processing the second set of columns.

9. The apparatus of claim 1 , wherein the ECC decoder is configured to artificially slow processing of the second set of columns by breaking the processing of the second set of columns into subprocesses and executing the subprocesses during different clock cycles.

10. The apparatus of claim 1 , wherein the ECC decoder is configured to use a single clock cycle to process one or more columns of the first set of columns.

11. The apparatus of claim 1 , wherein slowing processing of the second set of columns of the parity check matrix has a lower peak to average power ratio than using a single clock cycle to process the second set of columns of the parity check matrix.

12. A method comprising:
reading data stored by a non-volatile memory device;
processing a first set of columns of a parity check matrix for the data at a first speed; and
processing a second set of columns of the parity check matrix for the data at a slower speed than the first speed, the second set of columns having higher column weights than the first set of columns.

13. The method of claim 12 , wherein the second set of columns is processed at a slower speed than the first speed by using only a subset of available processing units to process the second set of columns such that one or more other processing units are idle.

14. The method of claim 12 , wherein the second set of columns is processed at a slower speed than the first speed by reducing a number of messages calculated per bit per clock cycle for the second set of columns compared to a number of messages calculated per bit per clock cycle for the first set of columns.

15. The method of claim 12 , further comprising encoding the data for storage by the non-volatile memory device by enforcing a maximum number of edges in a window of clock cycles to slow the processing of the second set of columns of the parity check matrix.

16. The method of claim 12 , wherein the second set of columns is processed at a slower speed than the first speed by waiting a number of clock cycles without processing a column of the parity check matrix.

17. The method of claim 12 , wherein the second set of columns is processed at a slower speed than the first speed by rescheduling processing of the second set of columns such that one or more columns from the first set of columns are processed between the processing of columns of the second set of columns.

18. The method of claim 12 , further comprising temporally distributing processing of the second set of columns among processing units such that one or more columns from the first set of columns are processed by processing units disposed between processing units processing the second set of columns.

19. The method of claim 12 , wherein the second set of columns is processed at a slower speed than the first speed by breaking the processing of the second set of columns into subprocesses and executing the subprocesses during different clock cycles.

20. An apparatus comprising:
means for reading data stored by a non-volatile memory device;
means for processing a first set of columns of a low-density parity-check code matrix for the data at a first speed; and
means for processing a second set of columns of the matrix for the data at a slower speed than the first speed, the second set of columns having higher column weights than the first set of columns and the slower speed selected to maintain a peak to average power ratio below a power threshold.

Assignees

• Western Digital Tech Inc

Inventors

• Zamir Ran
• Avraham Dudy
• Sharon Eran
• Alrod Idan
• Goldenberg Idan
• Fainzilber Omer
• Ryabinin Yuri
• Dumchin Yan
• Mariasin Igal
• Banani Eran

Classifications

• G06F11/1048

  using arrangements adapted for a specific error detection or correction feature · CPC title

• H03M13/6502 Primary

  Reduction of hardware complexity or efficient processing · CPC title

• H03M13/616

  Matrix operations, especially for generator matrices or check matrices, e.g. column or row permutations · CPC title

• H03M13/3707 Primary

  Adaptive decoding and hybrid decoding, e.g. decoding methods or techniques providing more than one decoding algorithm for one code · CPC title

• H03M13/1131

  Scheduling of bit node or check node processing · CPC title