Storage device operations based on bit error rate (BER) estimate

Patent metadata

Field	Value
Publication number	US-10180874-B2
Application number	US-201715614140-A
Country	US
Kind code	B2
Filing date	Jun 5, 2017
Priority date	Oct 28, 2015
Publication date	Jan 15, 2019
Grant date	Jan 15, 2019

Abstract

A data storage device may include a memory and a controller that includes an error correction coding (ECC) decoder configured to operate in a plurality of decoding modes. The controller also includes a bit error rate estimator configured to determine, based on data received from the memory, bit error rate estimates for ECC codewords from the memory. The controller also includes a data path management unit configured to reorder the codewords based on the bit error rate estimates and to provide the reordered codewords to the ECC decoder.

First claim

What is claimed is:

1. A data storage device comprising:
a memory; and
a controller including:
an error correction coding (ECC) decoder configured to operate in a plurality of decoding modes;
a bit error rate estimator configured to determine, based on data received from the memory, bit error rate estimates for codewords from the memory; and
a data path management unit configured to reorder the codewords based on the bit error rate estimates and to provide the reordered codewords to the ECC decoder.

2. The data storage device of claim 1 , wherein reordering the codewords reduces average decoding latency of the codewords as compared to decoding the codewords according to an order that the codewords are received, by the controller, from the memory.

3. The data storage device of claim 1 , further comprising a first queue coupled to the ECC decoder.

4. The data storage device of claim 3 , wherein the data path management unit is further configured to reorder the codewords to position codewords with lower bit error rate estimates closer to a front of the first queue than codewords with higher bit error rate estimates.

5. The data storage device of claim 4 , wherein the data path management unit is further configured to:
determine, for each of the codewords, a delay estimate indicating how long the codeword will remain in the first queue;
compare the delay estimates to a delay threshold; and
in response to one or more of the delay estimates exceeding the delay threshold, move the one or more codewords associated with the one or more of the delay estimates closer to the front of the first queue.

6. The data storage device of claim 3 , further comprising a second queue, wherein the data path management unit is further configured to:
determine, for each of the codewords, a decoding mode associated with the codeword;
in response to one or more of the codewords being associated with a first decoding mode, insert the one or more of the codewords that are associated with the first decoding mode into the first queue; and
in response to one or more of the codewords being associated with a second decoding mode, insert the one or more of the codewords that are associated with the second decoding mode into the second queue.

7. The data storage device of claim 6 , wherein in response to a failure to decode a particular codeword according to the first decoding mode, the data path management unit is further configured to insert the particular codeword into the second queue.

8. The data storage device of claim 7 , wherein the data path management unit is further configured to determine a position of the particular codeword in the second queue based on a bit error rate estimate of the particular codeword.

9. The data storage device of claim 8 , wherein the data path management unit is further configured to determine the position further based on a delay threshold.

10. The data storage device of claim 3 , wherein:
the ECC decoder includes:
a first decoder; and
a second decoder; and

the data path management unit is further configured to:
in response to detecting that a first codeword and a second codeword are to be decoded at the second decoder according to a second decoding mode and that other codewords are to be decoded at the first decoder according to a first decoding mode, to position one or more of the other codewords between the first codeword and the second codeword in the first queue;
dequeue the first codeword and initiate decode processing of the first codeword at the second decoder; and
while the decode processing of the first codeword is ongoing at the second decoder, sequentially dequeue and decode the one or more of the other codewords at the first decoder.

11. The data storage device of claim 1 , wherein the bit error rate estimates include syndrome weight.

12. A method comprising:
receiving error correction coding (ECC) codewords from a memory;
determining, based on data received from the memory, bit error rate estimates for the codewords;
reordering the codewords based on the bit error rate estimates; and
providing the reordered codewords to an ECC decoder that is configured to operate in a plurality of decoding modes.

13. The method of claim 12 , wherein reordering the codewords reduces average decoding latency of the codewords as compared to decoding the codewords according to a received order of the codewords.

14. The method of claim 12 , wherein reordering the codewords comprises:
determining a position of each of the codewords in a queue;
determining, for each of the codewords, a delay estimate indicating how long the codeword will remain in the queue; and
in response to one or more of the delay estimates exceeding a delay threshold, moving the one or more codewords associated with the one or more of the delay estimates closer to the front of the queue.

15. The method of claim 12 , further comprising:
determining, for each of the codewords, a decoding mode associated with the codeword;
in response to one or more of the codewords being associated with a first decoding mode, inserting the one or more of the codewords that are associated with the first decoding mode into a first queue;
in response to one or more of the codewords being associated with a second decoding mode, inserting the one or more of the codewords that are associated with the second decoding mode into the second queue; and
in response to a failure to decode a particular codeword according to the first decoding mode, inserting the particular codeword into a second queue.

16. The method of claim 12 , further comprising:
in response to detecting that a first codeword and a second codeword are to be decoded at a second decoder of the ECC decoder according to a second decoding mode and that other codewords are to be decoded at a first decoder of the ECC decoder according to a first decoding mode, positioning one or more of the other codewords between the first codeword and the second codeword in a queue;
dequeuing the first codeword and initiating decode processing of the first codeword at the second decoder; and
while the decode processing of the first codeword is ongoing at the second decoder, sequentially dequeuing and decoding the one or more of the other codewords at the first decoder.

17. An apparatus comprising:
means for storing data;
means for error correction coding (ECC) decoding in a plurality of decoding modes;
means for determining, based on data received from the means for storing data, bit error rate estimates for codewords from the means for storing data;
means for reordering the codewords based on the bit error rate estimates; and
means for providing the reordered codewords to the means for ECC decoding.

18. The apparatus of claim 17 , wherein the means for providing the reordered codewords includes means for enqueuing, the means for enqueuing coupled to the means for ECC decoding.

19. The apparatus of claim 18 , wherein the means for reordering is further configured to position codewords with lower bit error rate estimates closer to a front of the means for enqueuing than codewords with higher bit error rate estimates.

20. The apparatus of claim 18 , wherein:
the means for ECC decoding includes:
first means for decoding according to a first mode; and
second means for decoding according to a second mode; and

the means for providing the reordered codewords includes:
first means for enqueuing coupled to the first means for decoding; and
second means for enqueuing coupled to t

Assignees

• Western Digital Tech Inc

Inventors

• Bazarsky Alexander
• Sharon Eran
• Ryabinin Yuri
• Dumchin Yan
• Alrod Idan
• Navon Ariel

Classifications

• G06F11/1068

  in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence) · CPC title

• G06F3/064

  Management of blocks · CPC title

• H03M13/1102

  Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes · CPC title

• G06F11/1012 Primary

  using codes or arrangements adapted for a specific type of error (G06F11/1048 takes precedence) · CPC title

• H03M13/612

  Aspects specific to channel or signal-to-noise ratio estimation (H03M13/63 takes precedence) · CPC title