Ecc decoder with multiple decoding modes

Patent metadata

Field	Value
Publication number	US-2018159556-A1
Application number	US-201715613898-A
Country	US
Kind code	A1
Filing date	Jun 5, 2017
Priority date	Dec 1, 2016
Publication date	Jun 7, 2018
Grant date	—

Abstract

A device includes a low density parity check (LDPC) decoder that configured to receive a representation of a codeword. The LDPC decoder includes multiple data processing units (DPUs) and a control circuit. The control circuit is responsive to a decoding mode indicator and to an error metric and is configured to configure the DPUs according to a decoding mode indicated by the decoding mode indicator. The control circuit is further configured to selectively set a reduced-power configuration of one or more components of the LDPC decoder at least partially based on the error metric.

First claim

What is claimed is:

1 . A device comprising:
a non-volatile memory; and a low density parity check (LDPC) decoder configured to receive a representation of a codeword read from the non-volatile memory, the LDPC decoder comprising:
multiple data processing units (DPUs); and
a control circuit responsive to a decoding mode indicator and to an error metric associated with the representation of the codeword, the control circuit configured to:
configure the DPUs according to a decoding mode indicated by the decoding mode indicator; and
selectively set a reduced-power configuration of one or more components of the LDPC decoder at least partially based on the error metric.

2 . The device of claim 1 , wherein in the decoding mode a first number of the DPUs are enabled, and wherein in the reduced-power configuration a second number of DPUs are enabled, the second number less than the first number.

3 . The device of claim 1 , further comprising a decoder clock configured to generate a first clock signal having a first clock frequency in the decoding mode and to generate a second clock signal having a second clock frequency in the reduced-power configuration, the second clock frequency less than the first clock frequency.

4 . The device of claim 1 , further comprising a voltage supply coupled to the DPUs, the voltage supply configured to provide a first supply voltage to the DPUs in the decoding mode and to provide a second supply voltage to the DPUs in the reduced-power configuration, the second supply voltage less than the first supply voltage.

5 . The device of claim 1 , wherein the LDPC decoder is further configured to update the error metric during decoding of the representation of the codeword, and wherein the control circuit is further configured to selectively set the reduced-power configuration based on the updated error metric during the decoding of the representation of the codeword.

6 . The device of claim 1 , wherein the error metric includes a syndrome weight.

7 . The device of claim 1 , wherein the LDPC decoder further comprises:
a message memory configured to store decoding messages; and a reordering circuit coupled to the control circuit and configured to selectively reorder at least one of the decoding messages responsive to the decoding mode indicator.

8 . The device of claim 7 , wherein the reordering circuit is further configured to selectively reorder the at least one of the decoding messages in the reduced-power configuration.

9 . The device of claim 7 , wherein the LDPC decoder is further configured to process the representation of the codeword based on a quasi-cyclic LDPC (QC-LDPC) parity check matrix that has a first block matrix size associated with the decoding mode, and wherein the reordering circuit is further configured to selectively reorder the decoding messages in the reduced-power configuration to transform the QC-LDPC parity check matrix to a second QC-LDPC parity check matrix having a second block matrix size.

10 . A method comprising:
at a device including a non-volatile memory and a low density parity check (LDPC) decoder, the LDPC decoder including multiple data processing units (DPUs), performing:
receiving, at the LDPC decoder, a representation of a codeword read from the non-volatile memory;
enabling a number of the DPUs to decode the representation of the codeword responsive to a decoding mode indicator, wherein a first number of the DPUs corresponds to a first decoding mode and a second number of the DPUs corresponds to a second decoding mode; and
selectively setting a reduced-power configuration of one or more components of the LDPC decoder at least partially based on an error metric associated with the codeword.

11 . The method of claim 10 , wherein in the first decoding mode a first number of DPUs are enabled, and wherein in the reduced-power configuration a second number of DPUs are enabled, the second number less than the first number.

12 . The method of claim 10 , wherein in the first decoding mode the DPUs receive a first clock signal having a first clock frequency, and wherein in the reduced-power configuration the DPUs receive a second clock signal having a second clock frequency, the second clock frequency less than the first clock frequency.

13 . The method of claim 10 , wherein in the first decoding mode a first supply voltage is provided to the DPUs, and wherein in the reduced-power configuration a second supply voltage is provided to the DPUs, the second supply voltage less than the first supply voltage.

14 . The method of claim 10 , wherein the error metric includes a syndrome weight.

15 . The method of claim 10 , further comprising selectively reordering at least one decoding message according to a first degree of parallelism and responsive to the decoding mode indicator.

16 . The method of claim 10 , further comprising:
processing the representation of the codeword based on a quasi-cyclic LDPC (QC-LDPC) parity check matrix that has a first block matrix size associated with the decoding mode; and selectively reordering decoding messages in the reduced-power configuration to transform the QC-LDPC parity check matrix to a second QC-LDPC parity check matrix having a second block matrix size.

17 . An apparatus comprising:
means for non-volatile storage; and means for low density parity check (LDPC) decoding, the means for LDPC decoding comprising:
multiple means for data processing; and
means for enabling decoding of a representation of a codeword according to a decoding mode indicated by a decoding mode indicator and for selectively setting a reduced-power configuration of one or more components of the means for LDPC decoding at least partially based on an error metric.

18 . The apparatus of claim 17 , wherein in the decoding mode a first number of the means for data processing are enabled, and wherein in the reduced-power configuration a second number of the means for data processing are enabled, the second number less than the first number.

19 . The apparatus of claim 17 , further comprising means for providing a first clock signal having a first clock frequency in the decoding mode and for providing a second clock signal having a second clock frequency in the reduced-power configuration, the second clock frequency less than the first clock frequency.

20 . The apparatus of claim 17 , further comprising means for supplying a first supply voltage to the multiple means for data processing in the decoding mode and for supplying a second supply voltage to the multiple means for data processing in the reduced-power configuration, the second supply voltage less than the first supply voltage.

Assignees

• Western Digital Tech Inc

Inventors

• Dumchin Yan
• Ryabinin Yuri

Classifications

• H03M13/255 Primary

  with Low Density Parity Check [LDPC] codes · CPC title

• H03M13/1168

  wherein the sub-matrices have column and row weights greater than one, e.g. multi-diagonal sub-matrices · CPC title

• H03M13/6508 Primary

  Flexibility, adaptability, parametrability and configurability of the implementation · CPC title

• H03M13/3707

  Adaptive decoding and hybrid decoding, e.g. decoding methods or techniques providing more than one decoding algorithm for one code · CPC title

• H03M13/1108

  Hard decision decoding, e.g. bit flipping, modified or weighted bit flipping · CPC title