Statistical design with importance sampling reuse
US-11372701-B2 · Jun 28, 2022 · US
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Radens Carl J patents
Radens Carl J is listed as an inventor on 86 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Radens Carl J |
| Total patents | 86 |
| First publication | Jan 1, 2015 |
| Latest publication | Jun 28, 2022 |
Notable patents
Publications ranked by popularity score, then publication date.
Self-aligned via interconnect structures
US-11348832-B2 · May 31, 2022 · US
Forming self-aligned vias and air-gaps in semiconductor fabrication
US-2021202313-A1 · Jul 1, 2021 · US
Forming self-aligned vias and air-gaps in semiconductor fabrication
US-10930553-B2 · Feb 23, 2021 · US
Self-aligned via interconnect structures
US-10727122-B2 · Jul 28, 2020 · US
FinFET vertical flash memory
US-10707224-B2 · Jul 7, 2020 · US
Overturned thin film device with self-aligned gate and source/drain (S/D) contacts
US-10700214-B2 · Jun 30, 2020 · US
Structure for reduced source and drain contact to gate stack capacitance
US-10546936-B2 · Jan 28, 2020 · US
Statistical Design with Importance Sampling Reuse
US-2019370100-A1 · Dec 5, 2019 · US
Self-aligned via interconnect structures
US-2019326170-A1 · Oct 24, 2019 · US
Recent patents
Latest publications not already listed above.
Self-aligned via interconnect structures
US-10395984-B2 · Aug 27, 2019 · US
Self-aligned three dimensional chip stack and method for making the same
US-10388639-B2 · Aug 20, 2019 · US
Statistical design with importance sampling reuse
US-10387235-B2 · Aug 20, 2019 · US
Structure for reduced source and drain contact to gate stack capacitance
US-10374046-B2 · Aug 6, 2019 · US
Self-aligned three dimensional chip stack and method for making the same
US-10347617-B2 · Jul 9, 2019 · US
Structure for reduced source and drain contact to gate stack capacitance
US-2019189760-A1 · Jun 20, 2019 · US
Photovoltaic module with a controllable infrared protection layer
US-10319870-B2 · Jun 11, 2019 · US
Forming self-aligned vias and air-gaps in semiconductor fabrication
US-2019172748-A1 · Jun 6, 2019 · US
Self-aligned three dimensional chip stack and method for making the same
US-10304815-B2 · May 28, 2019 · US
Structure for reduced source and drain contact to gate stack capacitance
US-10269905-B2 · Apr 23, 2019 · US
Forming self-aligned vias and air-gaps in semiconductor fabrication
US-10242911-B2 · Mar 26, 2019 · US
Integrated circuit structure including via interconnect structure abutting lateral ends of metal lines and methods of forming same
US-10157832-B2 · Dec 18, 2018 · US
Method for producing self-aligned line end vias and related device
US-10115633-B2 · Oct 30, 2018 · US
Forming self-aligned vias and air-gaps in semiconductor fabrication
US-2018286750-A1 · Oct 4, 2018 · US
Finfet vertical flash memory
US-2018269220-A1 · Sep 20, 2018 · US
Intergrated circuit structure including via interconnect structure abutting lateral ends of metal lines and methods of forming same
US-2018261536-A1 · Sep 13, 2018 · US
Structure and process for overturned thin film device with self-aligned gate and s/d contacts
US-2018226511-A1 · Aug 9, 2018 · US
Structure and process for overturned thin film device with self-aligned gate and S/D contacts
US-10026849-B2 · Jul 17, 2018 · US
Semiconductor devices
US-10008500-B2 · Jun 26, 2018 · US
FinFET vertical flash memory
US-10002876-B2 · Jun 19, 2018 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| IBM | 68 |
| St Microelectronics Inc | 20 |
| Globalfoundries Inc | 17 |
| Radens Carl J | 5 |
| Tessera Inc | 2 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| H10D84/038 | 28 |
| H10W20/42 | 23 |
| H10W20/43 | 22 |
| H01L23/5226 | 22 |
| H10P50/73 | 20 |