Forming self-aligned vias and air-gaps in semiconductor fabrication

Patent metadata

Field	Value
Publication number	US-10242911-B2
Application number	US-201715815173-A
Country	US
Kind code	B2
Filing date	Nov 16, 2017
Priority date	Mar 29, 2017
Publication date	Mar 26, 2019
Grant date	Mar 26, 2019

Abstract

A semiconductor device includes a first trench on a mandrel line through a top mask layer and stopping at a middle mask layer; and a second trench on a non-mandrel line through the top mask layer and stopping at the middle mask layer. A spacer material is removed from a structure resulting from etching the first trench and the second trench. The device includes a first via structure, formed using a removable material, in the first trench; a second via structure, formed using a removable material, in the second trench; an air-gap formed in a third trench created at a location of the spacer; a fourth trench formed by etching, to remove the first via structure and a first portion of a bottom mask layer under the first via structure; and a self-aligned line-end via on the mandrel line formed by filling the fourth trench with a conductive metal.

First claim

What is claimed is:

1. A method comprising:
etching a first trench at a first location on a mandrel line in a set of mandrel lines, through a top mask layer and stopping at a middle mask layer;
etching a second trench at a second location on a non-mandrel line in a set of non-mandrel lines, through the top mask layer and stopping at the middle mask layer;
removing a spacer material from a structure resulting from etching the first trench and the second trench;
forming, using a removable material, a first via structure in the first trench and second via structure in the second trench;
forming an air-gap in a third trench created at a location of the spacer;
etching, to remove the first via structure and a first portion of a bottom mask layer under the first via structure, to form a fourth trench; and
filling the fourth trench with a conductive metal to form a self-aligned line-end via on the mandrel line.

2. The method of claim 1 , further comprising:
etching, to remove the second via structure and a second portion of the bottom mask layer under the second via structure, to form a fifth trench; and
filling the fifth trench with the conductive metal to form a self-aligned inline via on the non-mandrel line.

3. The method of claim 1 , wherein the air-gap is aligned with the first via structure and the second via structure.

4. The method of claim 1 , further comprising:
filling the third trench with a low resistance material such that a hollow space is encapsulated within the low resistance material, the hollow space forming the air-gap.

5. The method of claim 1 , further comprising:
stopping, as a part of etching the third trench, the third trench at the bottom mask layer.

6. The method of claim 1 , further comprising:
stopping, as a part of etching the third trench, the third trench at the middle mask layer.

7. The method of claim 1 , wherein the second via structure and a third via structure are both inline vias, wherein the second via structure is aligned with the third via structure, and wherein the second via structure and the third via structure are both aligned with the non-mandrel line.

8. The method of claim 1 , wherein the first via structure and a third via structure are both line-end vias, wherein the first via structure is aligned with the third via structure, and wherein the first via structure and the third via structure are both aligned with the mandrel line.

9. The method of claim 1 , further comprising:
separating two adjacent vias in the mandrel line with an intervening dielectric structure extending from the middle mask layer to the top mask layer.

10. The method of claim 1 , further comprising:
filling the first trench and the second trench with the removable material up to the top mask layer.

11. The method of claim 1 , further comprising:
forming, in the structure, above the bottom mask layer, a first layer of a first material topped by the middle mask layer; and
forming, above the middle mask layer, a second layer of a second material topped by the top mask layer.

12. The method of claim 1 , further comprising:
removing the top mask layer from above the spacer; and
etching to create the third trench at the location of the spacer.

13. The method of claim 1 , further comprising:
locating, in a structure, the set of mandrel lines, the set of non-mandrel lines, and a set of spacers, the structure comprising the bottom mask layer, a first layer, the middle mask layer, a second layer, and the top mask layer, and wherein a spacer in the set of spacers comprises a structure formed above the top mask layer.

14. A computer usable program product comprising a computer readable storage medium, and program instructions stored on the computer readable storage medium, the stored program instructions comprising:
program instructions to etch a first trench at a first location on a mandrel line in a set of mandrel lines, through a top mask layer and stopping at a middle mask layer;
program instructions to etch a second trench at a second location on a non-mandrel line in a set of non-mandrel lines, through the top mask layer and stopping at the middle mask layer;
program instructions to remove a spacer material from a structure resulting from etching the first trench and the second trench;
program instructions to form, using a removable material, a first via structure in the first trench and second via structure in the second trench;
program instructions to form an air-gap in a third trench created at a location of the spacer;
program instructions to etch, to remove the first via structure and a first portion of a bottom mask layer under the first via structure, to form a fourth trench; and
program instructions to fill the fourth trench with a conductive metal to form a self-aligned line-end via on the mandrel line.

15. A semiconductor device comprising:
a first trench etched at a first location on a mandrel line in a set of mandrel lines, through a top mask layer and stopping at a middle mask layer;
a second trench etched at a second location on a non-mandrel line in a set of non-mandrel lines, through the top mask layer and stopping at the middle mask layer, wherein a spacer material is removed from a structure resulting from etching the first trench and the second trench;
a first via structure, formed using a removable material, in the first trench;
a second via structure, formed using a removable material, in the second trench;
an air-gap formed in a third trench created at a location of the spacer;
a fourth trench formed by etching, to remove the first via structure and a first portion of a bottom mask layer under the first via structure; and
a self-aligned line-end via on the mandrel line formed by filling the fourth trench with a conductive metal.

16. The semiconductor device of claim 15 , further comprising:
a fifth trench formed by etching, to remove the second via structure and a second portion of the bottom mask layer under the second via structure; and
a self-aligned inline via on the non-mandrel line formed by filling the fifth trench with the conductive metal.

17. The semiconductor device of claim 15 , wherein the air-gap is aligned with the first via structure and the second via structure.

18. The semiconductor device of claim 15 , further comprising:
a low resistance material filling the third trench such that a hollow space is encapsulated within the low resistance material, the hollow space forming the air-gap.

19. The semiconductor device of claim 15 , wherein as a part of etching the third trench, the third trench is stopped at the bottom mask layer.

20. The semiconductor device of claim 15 , wherein as a part of etching the third trench, the third trench is stopped at the middle mask layer.

Assignees

• IBM

Inventors

• Clevenger Lawrence A
• Radens Carl J
• Zhang John H

Classifications

• H10W20/0693

  by forming self-aligned vias · CPC title

• H10P50/283

  by chemical means · CPC title

• H10P50/73

  using masks for insulating materials · CPC title

• H10W20/098

  by filling between adjacent conductive parts · CPC title

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title