Finfet vertical flash memory

Patent metadata

Field	Value
Publication number	US-2018269220-A1
Application number	US-201815988828-A
Country	US
Kind code	A1
Filing date	May 24, 2018
Priority date	Oct 29, 2014
Publication date	Sep 20, 2018
Grant date	—

Abstract

A plurality of fin structures containing, from bottom to top, a non-doped semiconductor portion and a second doped semiconductor portion of a first conductivity type, extend upwards from a surface of a first doped semiconductor portion of the first conductivity type. A trapping material (e.g., an electron-trapping material) is present along a bottom portion of sidewall surfaces of each non-doped semiconductor portion and on exposed portions of each first doped semiconductor portion. Functional gate structures straddle each fin structure. Metal lines are located above each fin structure and straddle each functional gate structure. Each metal line is orientated perpendicular to each functional gate structure and has a bottommost surface that is in direct physical contact with a portion of a topmost surface of each of the second doped semiconductor portions.

First claim

What is claimed is:

1 . A method of forming a semiconductor structure, the method comprising:
forming a plurality of fin structures on a surface of a first doped semiconductor layer of a first conductivity type, wherein each fin structure of the plurality of fin structures includes from bottom to top, a non-doped semiconductor portion and a second doped semiconductor portion of the first conductivity type; forming a first sacrificial spacer surrounding each fin structure; patterning the first doped semiconductor layer not protected by the fin structure and the first sacrificial spacer to provide a plurality of first doped semiconductor portions beneath each fin structure; removing the first sacrificial gate spacer from each fin structure; forming a dielectric material layer between each fin structure and on a topmost surface of each first doped semiconductor portion; forming a second sacrificial spacer surrounding each fin structure and located on a topmost surface of the dielectric material layer; removing the dielectric material layer to expose a bottom sidewall surface of each non-doped semiconductor portion of each fin structure; forming a trapping material on the exposed bottom sidewall surface of each non-doped semiconductor fin portion; removing the second sacrificial spacer; and forming a plurality of function gate structures straddling each fin structure of the plurality of fin structures.

2 . The method of claim 1 , further comprising forming a plurality of metal lines located above each fin structure of the plurality of fin structures and straddling each functional gate structure of the plurality of functional gate structures, wherein each metal line is orientated perpendicular to each functional gate structure.

3 . The method of claim 2 , wherein each metal line has a bottommost surface that is in direct physical contact with a portion of a topmost surface of each of the second doped semiconductor portions.

4 . The method of claim 2 , wherein the trapping material layer is an electron-trapping material.

5 . The method of claim 4 , wherein the electron-trapping material is a doped metal oxide, or a doped metal nitride.

6 . The method of claim 1 , wherein the forming the plurality of fin structure comprises:
epitaxially depositing a semiconductor material stack on a surface of a bulk semiconductor substrate, wherein the semiconductor material stack comprises, from bottom to top, a first doped semiconductor layer of the first conductivity type, a non-doped semiconductor layer, and a second doped semiconductor layer of the first conductivity type; forming a hard mask layer on an uppermost surface of the semiconductor material stack; and patterning the hard mask layer, the second doped semiconductor layer and the non-doped semiconductor layer.

7 . The method of claim 6 , wherein the patterning comprises a sidewall image transfer process.

8 . The method of claim 6 , further comprising forming a doped region of a second conductivity type that is opposite to the first conductivity into an exposed portion of the bulk semiconductor substrate and between each of the first doped semiconductor portions.

9 . The method of claim 8 , further comprising forming a trench isolation structure between each of the first doped semiconductor portions.

10 . The method of claim 9 , wherein the trench isolation structure has a topmost surface that is coplanar with a topmost surface of each first doped semiconductor portion and a bottommost surface that is present in the doped region.

11 . The method of claim 1 , wherein the first conductivity type is p-type, and the first doped semiconductor layer, the non-doped semiconductor layer, and the second doped semiconductor layer each comprise silicon.

12 . The method of claim 1 , wherein the first conductivity type is n-type, and the first doped semiconductor layer, the non-doped semiconductor layer, and the second doped semiconductor layer each comprise silicon.

13 . The method of claim 1 , wherein each functional gate structure includes a gate dielectric material portion and a gate conductor portion, and wherein the gate dielectric material portion is in direct physical contact with sidewalls of each fin structures and in direct physical contact with another portion of the second doped semiconductor portion of each fin structure.

14 . The method of claim 13 , wherein a portion of the gate dielectric material portion is located on a surface of the trapping material.

15 . The method of claim 1 , wherein the sidewall surfaces of each non-doped semiconductor portion is vertically aligned to sidewall surfaces of the second doped semiconductor portion.

16 . The method of claim 1 , wherein each non-doped semiconductor region has an epitaxial relationship with the first doped semiconductor portion, and each second doped semiconductor portion has an epitaxial relationship with the non-doped semiconductor portion.

17 . The method of claim 1 , wherein the trapping material layer comprises a material that is conductive to electron or hole trapping within the grain boundaries of the material.

18 . The method of claim 9 , wherein the trapping material layer is in direct physical contact with an entirety of the bottom portion of sidewall surfaces of each non-doped semiconductor portion of each fin structure and in direct physical contact with an entire exposed topmost surface of each first doped semiconductor portion and an entire exposed topmost surface of each trench isolation structure.

19 . The method of claim 1 , wherein the trapping material layer is in direct physical contact with an entirety of the bottom portion of sidewall surfaces of each non-doped semiconductor portion of each fin structure and in direct physical contact with an entire exposed topmost surface of each first doped semiconductor portion.

20 . The method of claim 19 , wherein the trapping material layer further has a topmost surface that is located beneath a topmost surface of the non-doped semiconductor portion of each of the fin structures.

Assignees

• IBM

Inventors

• Divakaruni Ramachandra
• Kumar Arvind
• Radens Carl J

Classifications

• H01L27/0886

  Electricity · mapped topic

• H01L21/823431

  Electricity · mapped topic

• H01L27/1203

  Electricity · mapped topic

• H01L29/408

  Electricity · mapped topic

• H01L21/28282

  Electricity · mapped topic