Forming self-aligned vias and air-gaps in semiconductor fabrication

Patent metadata

Field	Value
Publication number	US-2021202313-A1
Application number	US-202117181399-A
Country	US
Kind code	A1
Filing date	Feb 22, 2021
Priority date	Mar 29, 2017
Publication date	Jul 1, 2021
Grant date	—

Abstract

A semiconductor device includes a first trench on a mandrel line through a top mask layer and stopping at a middle mask layer; and a second trench on a non-mandrel line through the top mask layer and stopping at the middle mask layer. A spacer material is removed from a structure resulting from etching the first trench and the second trench. The device includes a first via structure, formed using a removable material, in the first trench; a second via structure, formed using a removable material, in the second trench; an air-gap formed in a third trench created at a location of the spacer; a fourth trench formed by etching, to remove the first via structure and a first portion of a bottom mask layer under the first via structure; and a self-aligned line-end via on the mandrel line formed by filling the fourth trench with a conductive metal.

First claim

What is claimed is:

1 . A method comprising:
providing a substrate; providing a structure disposed above the substrate, the structure comprising one or more material layers; providing a plurality of spacers disposed above the structure, the plurality of spacers extending in a direction parallel to the substrate; etching, using the plurality of spacers as a mask, (i) first trenches in the structure to a first level above the substrate and (ii) second trenches in the structure to the first level above the substrate, the second trenches alternating with the first trenches; filling the first trenches and second trenches with a first material; etching a plurality of first self-aligned via openings through the first material in the first trenches to a second level above the substrate, the second level being closer to the substrate than the first level; filling the plurality of first self-aligned via openings with a second material; etching a plurality of second self-aligned via openings through the first material in the second trenches down to approximately the second level above the substrate; and filling the plurality of second self-aligned via openings with a third material.

2 . The method of claim 1 , wherein:
the structure comprises an upper hardmask layer; and the method further comprises, subsequent to etching the first trenches and second trenches, removing the spacers to reveal the upper hardmask layer at an exposed top surface of the structure.

3 . The method of claim 2 , further comprising:
subsequent to etching the first trenches and second trenches and removing the spacers to reveal the upper hardmask layer, depositing a liner to protect the exposed top surface of the structure.

4 . The method of claim 2 , further comprising:
removing the upper hardmask layer.

5 . The method of claim 1 , further comprising:
subsequent to filling the first trenches and second trenches with the first material, replacing portions of the first material in one or more of the first trenches or the second trenches with a line-end dielectric material.

6 . The method of claim 5 , wherein two first self-aligned via openings or two second self-aligned via openings are disposed adjacent to opposite sides of a region of line-end dielectric material.

7 . The method of claim 1 , wherein the structure comprises a first etch stop layer, wherein the first level above the substrate corresponds to the first etch stop layer.

8 . The method of claim 7 , wherein the structure comprises a second etch stop layer, wherein the second level above the substrate corresponds to the second etch stop layer.

9 . The method of claim 1 , further comprising:
removing one or more portions of the structure in regions between adjacent first and second trenches to approximately the first level above the substrate to form third trenches.

10 . The method of claim 9 , further comprising:
depositing a dielectric layer in the third trenches to form an airgap.

11 . The method of claim 10 , further comprising:
removing the first material, the second material, and the third material; and filling (i) the first trenches, (ii) the second trenches, (iii) the third trenches, (iv) the plurality of first self-aligned via openings, and (v) the plurality of second self-aligned via openings with metal.

12 . The method of claim 10 , wherein the dielectric layer comprises silicon and carbon.

13 . The method of claim 10 , wherein the dielectric layer comprises silicon and boron.

14 . The method of claim 10 , wherein the dielectric layer comprises silicon, carbon, nitrogen, and boron.

15 . The method of claim 1 , further comprising:
removing portions of the structure in regions between the first trenches and second trenches to below the first level above the substrate to form third trenches.

16 . The method of claim 15 , further comprising:
depositing a dielectric layer in the third trenches to form an airgap.

17 . The method of claim 16 , further comprising:
removing the first material, the second material, and the third material; and filling (i) the first trenches, (ii) the second trenches, (iii) the third trenches, (iv) the plurality of first self-aligned via openings, and (v) the plurality of second self-aligned via openings with metal.

18 . The method of claim 16 , wherein the dielectric layer comprises silicon and carbon.

19 . The method of claim 16 , wherein the dielectric layer comprises silicon and boron.

20 . The method of claim 16 , wherein the dielectric layer comprises silicon, carbon, nitrogen, and boron.

21 . The method of claim 1 , further comprising:
removing the first material, the second material, and the third material; and filling (i) the first trenches, (ii) the second trenches, (iii) the plurality of first self-aligned via openings, and (iv) the plurality of second self-aligned via openings with metal.

Assignees

• Tessera Inc

Inventors

• Clevenger Lawrence A
• Radens Carl J
• Zhang John H

Classifications

• H10W20/0693

  by forming self-aligned vias · CPC title

• H10P50/283

  by chemical means · CPC title

• H10P50/73

  using masks for insulating materials · CPC title

• H10W20/098

  by filling between adjacent conductive parts · CPC title

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title