Structure for reduced source and drain contact to gate stack capacitance

Patent metadata

Field	Value
Publication number	US-10374046-B2
Application number	US-201715396796-A
Country	US
Kind code	B2
Filing date	Jan 2, 2017
Priority date	Dec 17, 2015
Publication date	Aug 6, 2019
Grant date	Aug 6, 2019

Abstract

A structure of a semiconductor device is described. In one aspect of the invention, a FinFET semiconductor device includes a FinFET transistor which includes a source region and a drain region disposed in a fin on a first surface of a substrate. A gate structure is disposed over a central portion of the fin. A wiring layer of conductive material is disposed over a second surface of the substrate which is opposite to the first surface of the substrate. A set of contact studs include a first contact stud which extends completely through the height of the fin in the source region and the substrate to the wiring layer. The set of contact studs also includes a second contact stud which extends completely through the height of the fin in the drain region and the substrate to the wiring layer. In other aspects of the invention, the device is a Nanosheet device or an inverter.

First claim

Having described our invention, what we now claim is as follows:

1. A FinFET semiconductor device comprising:
a FinFET transistor including a source region and a drain region disposed in a fin on a first surface of a substrate, wherein the transistor further includes a gate structure disposed over a central portion of the fin;
a wiring layer of conductive material disposed over a second surface of the substrate, the second surface of the substrate opposite to the first surface of the substrate; and
a set of contact studs including a first contact stud extending completely through a height of the fin in the source region and extending through the substrate to a first respective portion of the wiring layer and a second contact stud extending completely through a height of the fin in the drain region and extending through the substrate to a second respective portion of the wiring layer, wherein the contact studs are comprised of a metal.

2. The device as recited in claim 1 , further comprising crystalline silicon grown over the source and drain regions of the fin.

3. The device as recited in claim 2 , wherein the first contact stud and the second contact stud respectively extend through the crystalline silicon grown over the source and drain regions of the fin.

4. The device as recited in claim 1 , wherein the substrate comprises a layer of buried oxide dielectric material disposed between the transistor and a second layer of the substrate layer.

5. The device as recited in claim 1 , wherein the first contact stud electrically connects the source region in the fin to the first respective portion of the wiring layer on the second surface of the substrate and the second contact stud electrically connects the drain region in the fin to the second respective portion of the wiring layer.

6. The device as recited in claim 1 , wherein the set of contact studs are coated by an isolation layer in a semiconductor substrate layer and are free of the isolation layer in the source region and the drain region.

7. The device as recited in claim 1 , wherein a first end of each of the first and second contact studs terminates at a top surface of the fin.

Assignees

• IBM

Inventors

• Radens Carl J
• Williams Richard Q

Classifications

• H10W20/0245

  comprising use of blind vias during the manufacture · CPC title

• H10W20/0249

  wherein the through-semiconductor via protrudes from backsides of the chips, wafers or substrates during the manufacture · CPC title

• H10W20/481

  on the rear surfaces of the wafers or substrates · CPC title

• H10W20/218

  in silicon-on-insulator [SOI] wafers · CPC title

• H10P72/7422

  used to protect an active side of a device or wafer · CPC title