Overturned thin film device with self-aligned gate and source/drain (S/D) contacts

Patent metadata

Field	Value
Publication number	US-10700214-B2
Application number	US-201815945937-A
Country	US
Kind code	B2
Filing date	Apr 5, 2018
Priority date	Dec 2, 2015
Publication date	Jun 30, 2020
Grant date	Jun 30, 2020

Abstract

Processes and overturned thin film device structures generally include a gate having a concave shape defined by three faces. The processes generally include forming the overturned thin film device structures such that the channel self-aligns to the gate and the source/drain contacts include a self-aligned step height.

First claim

What is claimed is:

1. A thin film device structure, comprising:
a gate structure having a concave shape defined by three faces;
a gate insulating layer formed on opposite sidewalls and a bottom surface of the gate structure;
a channel comprising an amorphous metal oxide material, the channel formed on the gate insulating layer, the channel having a concave shape, wherein a first end portion and a second end portion of the channel extend over a topmost portion of the gate insulating layer;
a source region coupled to the first end portion of the channel, the source region comprising a first portion directly on a topmost surface of the first end portion of the channel, the first portion extending over the gate structure; and
a drain region coupled to the second end portion of the channel, the drain region comprising a first portion directly on a topmost surface of the second end portion of the channel, the first portion extending over the gate structure.

2. The thin film device of claim 1 , wherein the source region and the drain region are electrically coupled to the first and second end portions of the channel via a self-aligned width (t).

3. The thin film device of claim 2 , wherein the source region and the drain region include a conductive material that comprises nickel (Ni), silver (Ag), gold (Au), palladium (Pd), cobalt (Co), copper (Cu), iron, (Fe), aluminum (Al), chromium (Cr), platinum (Pt), tungsten (W), and combinations thereof.

4. The thin film device of claim 1 , wherein the amorphous metal oxide material comprises indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), indium zinc tin oxide (IZTO,) or indium oxide (In2O3).

5. The thin film device of claim 1 , further comprising a flexible substrate.

6. The thin film device of claim 5 , further comprising a liner disposed between the flexible substrate and the gate structure, wherein the liner comprises one or more of titanium (Ti), tantalum (Ta), ruthenium (Ru), iridium (Ir), cobalt (Co) and nitrides thereof.

7. The thin film device of claim 1 , wherein the gate insulating layer comprises hafnium oxide, aluminum oxide, silicon nitride or a combination thereof.

Assignees

• IBM
• St Microelectronics Inc

Inventors

• Clevenger Lawrence A
• Radens Carl J
• Xu Yiheng
• Zhang John H

Classifications

• H10D99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10D86/411

  characterised by materials, geometry or structure of the substrates · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• H10D84/0135

  Manufacturing their gate conductors · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title