Self-aligned three dimensional chip stack and method for making the same

Patent metadata

Field	Value
Publication number	US-10304815-B2
Application number	US-201715802541-A
Country	US
Kind code	B2
Filing date	Nov 3, 2017
Priority date	Dec 2, 2015
Publication date	May 28, 2019
Grant date	May 28, 2019

Abstract

Self-aligned three dimensional vertically stacked chip stacks and processes for forming the same generally include two or more vertically stacked chips supported by a scaffolding structure, the scaffolding structure defined by a first scaffolding trench and at least one additional scaffolding trench, the first scaffolding trench comprising a bottom surface having a width and a sidewall having a height extending from the bottom surface to define a lowermost trench in a scaffolding layer, the at least one additional scaffolding trench overlaying the first scaffolding trench having a sidewall having a height and a width, wherein the width of the at least one scaffolding trench is greater than the first scaffolding trench width to define a first stair between the first scaffolding trench and the at least one additional trench; a first chip secured to the first scaffolding trench having a height less than the first scaffolding trench sidewall height; and at least one additional chip secured to and supported by the first stair, wherein the at least one additional chip is vertically spaced apart from the first chip.

First claim

What is claimed is:

1. A three dimensional vertical chip stack comprising:
two or more vertically stacked chips supported by a scaffolding structure, the scaffolding structure defined by a first scaffolding trench and at least one additional scaffolding trench, the first scaffolding trench comprising a bottom surface having a width and a sidewall having a height extending from the bottom surface to define a lowermost trench in a scaffolding layer, the at least one additional scaffolding trench overlaying the first scaffolding trench having a sidewall having a height and a width, wherein the width of the at least one additional scaffolding trench is greater than the first scaffolding trench width to define a first stair between the first scaffolding trench and the at least one additional scaffolding trench;
a conformal adhesive liner on surfaces defining the first scaffolding trench and the at least one additional scaffolding trench;
a first chip secured via the conformal adhesive liner to the first scaffolding trench having a height less than the first scaffolding trench sidewall height; and
at least one additional chip secured via the conformal adhesive liner to and supported by the first stair, wherein the at least one additional chip is vertically spaced apart from the first chip by an interposer, wherein the first chip and the at least one additional chip are each self-aligned within the first scaffolding trench and the at least one additional scaffolding trench, respectively.

2. The three dimensional vertical chip stack of claim 1 , wherein the interposer is silicon.

3. The three dimensional vertical chip stack of claim 1 , further comprising a plurality of through silicon vias (TSVs) including a conductive material therein electrically connecting the first chip and the at least one additional chip, wherein the through silicon vias connect from an anchor pad to a body of the first chip and from the first chip to the body at least one additional chip.

4. The three dimensional vertical chip stack of claim 3 , wherein the through silicon vias connect to the body of the first chip and an edge of the at least one additional chip.

5. The three dimensional vertical chip stack of claim 1 , wherein the scaffolding layer is an elastic material.

6. The three dimensional vertical chip stack of claim 3 , wherein the anchor pad comprises copper.

7. The three dimensional vertical chip stack of claim 3 , wherein the anchor pad is at a thickness of 10 nanometers (nm) to 50 microns (μm).

8. The three dimensional vertical chip stack of claim 1 , further comprising at least one additional stair for every additional chip, wherein each chip has a height less than a respective sidewall height of a corresponding scaffolding trench.

9. The three dimensional vertical chip stack of claim 1 , wherein the interposer is a flowable liquid.

10. The three dimensional vertical chip stack of claim 1 , wherein the first chip and the at least one additional chip are different.

11. The three dimensional vertical chip stack of claim 1 , wherein the first chip and the at least one additional chip comprise flash memory chips, dynamic random access memory (DRAM) chips, or application specific integrated circuit (ASIC) chips.

Assignees

• IBM
• St Microelectronics Inc

Inventors

• Clevenger Lawrence A
• Radens Carl J
• Xu Yiheng
• Zhang John H

Classifications

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/732

  between stacked chips · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/288

  characterised by arrangements for thermal management of the stacked chips · CPC title

• H10W90/28

  the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape · CPC title