Structure for reduced source and drain contact to gate stack capacitance

Patent metadata

Field	Value
Publication number	US-10269905-B2
Application number	US-201715396787-A
Country	US
Kind code	B2
Filing date	Jan 2, 2017
Priority date	Dec 17, 2015
Publication date	Apr 23, 2019
Grant date	Apr 23, 2019

Abstract

A structure of a semiconductor device is described. A semiconductor device includes a transistor which further includes a gate structure, a source region and a drain region disposed on a first surface of a substrate. A wiring layer of conductive material is disposed over a second surface of the substrate. The second surface of the substrate is located opposite to the first surface of the substrate. A set of contact studs including a first contact stud which extends completely through the source region and through the substrate to a first respective portion of the wiring layer. The set of contact studs also includes a second contact stud which extends completely through the drain region and through the substrate to a second respective portion of the wiring layer.

First claim

Having described our invention, what we now claim is as follows:

1. A semiconductor device comprising:
a transistor including a gate structure, a source region and a drain region disposed on a first surface of a substrate;
a wiring layer of conductive material disposed over a second surface of the substrate, the second surface of the substrate opposite to the first surface of the substrate; and
a set of contact studs including a first contact stud extending completely through the source region and extending through the substrate to a first respective portion of the wiring layer and a second contact stud extending completely through the drain region and extending through the substrate to a second respective portion of the wiring layer.

2. The device as recited in claim 1 , wherein the device is a planar MOSFET device.

3. The device as recited in claim 1 , wherein the device further comprises a protective insulator layer disposed over the transistor and the set of contact studs extend through the protective insulator layer.

4. The device as recited in claim 1 , wherein the device further comprises an isolation layer comprised of silicon dioxide grown from the substrate in a thermal oxide process.

5. The device as recited in claim 1 , wherein the set of contact studs are composed of tungsten.

6. The device as recited in claim 1 , wherein a layer of dielectric material is disposed between the second surface of the substrate and the wiring layer.

7. The device as recited in claim 1 , wherein the wiring layer is composed of a metal selected from the group consisting of Cu, W, Al and a Cu alloy.

8. The device as recited in claim 1 , further comprising a protective insulator layer over the device structure disposed over the first surface of the substrate.

9. The device as recited in claim 1 , wherein the set of contact studs are composed of a material selected from the group of Ti, Mo, Pt and Co.

10. The device as recited in claim 1 , further comprising a set of contact metallurgy disposed between and in physical contact with the set of contact studs and the wiring layer, wherein an area of the wiring layer is larger than an area of the contact metallurgy.

11. The device as recited in claim 1 , wherein the first contact stud electrically connects the source region to the first respective portion of the wiring layer on the second surface of the substrate and the second contact stud electrically connects the drain region to the second respective portion of the wiring layer.

12. The device as recited in claim 3 wherein the protective insulator layer is conformally disposed over a gate portion of the transistor.

13. The device as recited in claim 1 , wherein the a set of contact studs are covered by an isolation layer in the substrate layer and are free of the isolation layer in the source region and the drain region.

Assignees

• IBM

Inventors

• Radens Carl J
• Williams Richard Q

Classifications

• H10W20/0245

  comprising use of blind vias during the manufacture · CPC title

• H10W20/0249

  wherein the through-semiconductor via protrudes from backsides of the chips, wafers or substrates during the manufacture · CPC title

• H10W20/481

  on the rear surfaces of the wafers or substrates · CPC title

• H10W20/218

  in silicon-on-insulator [SOI] wafers · CPC title

• H10P72/7422

  used to protect an active side of a device or wafer · CPC title