Self-aligned via interconnect structures

Patent metadata

Field	Value
Publication number	US-10727122-B2
Application number	US-201414563554-A
Country	US
Kind code	B2
Filing date	Dec 8, 2014
Priority date	Dec 8, 2014
Publication date	Jul 28, 2020
Grant date	Jul 28, 2020

Abstract

A self-aligned via interconnect structures and methods of manufacturing thereof are disclosed. The method includes forming a wiring structure in a dielectric material. The method further includes forming a cap layer over a surface of the wiring structure and the dielectric material. The method further includes forming an opening in the cap layer to expose a portion of the wiring structure. The method further includes selectively growing a metal or metal-alloy via interconnect structure material on the exposed portion of the wiring structure, through the opening in the cap layer. The method further includes forming an upper wiring structure in electrical contact with the metal or metal-alloy via interconnect structure.

First claim

What is claimed:

1. A method comprising:
forming a wiring structure in a dielectric material,
wherein forming the wiring structure comprises:
forming an opening in the dielectric material by an etching process;
depositing a barrier/liner material within the opening;
depositing a wiring material on the barrier/liner material and within the opening; and
removing residual barrier/liner material and wiring material from a top surface of the dielectric material by a planarizing process;

forming a cap layer over a surface of the planarized wiring structure and the dielectric material;
forming an opening in the cap layer to cross over a portion of the wiring structure which exposes the portion of the wiring structure;
selectively growing a metal or metal-alloy via interconnect structure directly on the exposed portion of the wiring structure and on a side surface of a portion of the cap layer adjacent to the opening, through the opening in the cap layer, with an upper portion of the metal or metal alloy via interconnect structure having exposed surfaces, wherein the selectively growing is performed while a top surface of the cap layer is exposed;
depositing a dielectric layer directly on both the exposed surfaces of the metal or metal-alloy via interconnect structure and an upper surface of the cap layer;
forming an opening in the dielectric layer to expose an upper surface and a first portion of a sidewall of the metal or metal-alloy via interconnect structure;
forming a barrier layer directly on the exposed upper surface and the first portion of the sidewall of the metal or metal-alloy via interconnect structure and on sidewalls of the opening in the dielectric layer, after the dielectric layer is opened so that the exposed one or more surfaces of the metal or metal alloy via interconnect structure are covered with the barrier layer, and other portions of the sidewall of the metal or metal alloy via interconnect structure which are not exposed from the dielectric layer are devoid of the barrier layer; and
forming an upper wiring structure in the opening of the dielectric layer over the barrier layer and extending over a plurality of surfaces of the metal or metal-alloy via interconnect structure, the upper wiring structure is formed aligned with a first side of the wiring structure and extending past a second side of the wiring structure, the upper wiring structure being formed in electrical contact with the metal or metal-alloy via interconnect structure directly on the barrier layer,
wherein the wiring material and the barrier/liner material are separated by a boundary, and
wherein a first vertical wall of the barrier/liner material of the wiring structure is aligned with a first vertical wall of the barrier layer which forms part of the upper wiring structure and a second vertical wall of the barrier/liner material of the wiring structure is not aligned with a second vertical wall of the barrier layer which forms part of the upper wiring structure.

2. The method of claim 1 , wherein the forming of the cap layer is a deposition of dielectric masking material.

3. The method of claim 1 , wherein the forming of the opening in the cap layer comprises forming a slot exposing the portion of the wiring structure.

4. The method of claim 3 , wherein the slot is formed orthogonal to the wiring structure.

5. The method of claim 1 , wherein an interface between the metal or metal-alloy via interconnect structure and the wiring structure is devoid of a barrier material and liner material.

6. The method of claim 5 , wherein the forming of the metal or metal-alloy via interconnect structure in the opening is a self aligned growth process of cobalt which overfills the opening.

7. The method of claim 6 , wherein the self aligned growth process of cobalt laterally overgrows over edges of the opening.

8. The method of claim 1 , wherein the forming of the upper wiring structure comprises:
etching a trench in the dielectric layer to form the opening and expose portions of the metal or metal-alloy via interconnect structure;
forming barrier material and liner material on the exposed portions of the metal or metal-alloy via interconnect structure and on sidewalls of the trench in the dielectric layer; and
forming a metal or metal-alloy material within the trench in the dielectric layer, on the liner material.

9. The method of claim 1 , further comprising cleaning oxide from the exposed portion of the wiring structure.

10. A method, comprising:
forming a wiring structure by depositing a wiring material on a barrier/liner material within a dielectric material;
forming a dielectric masking layer over the wiring structure and the dielectric material;
forming an opening in the dielectric masking layer, exposing a portion of the wiring structure;
overfilling the opening with a lateral overgrowth of metal or metal-alloy material to overlap edges of the opening and onto the dielectric masking layer by a defined distance which equals an overlap of an upper wiring structure and form a via interconnect structure in direct electrical contact with the wiring structure;
selectively growing the via interconnect structure directly on the exposed portion of the wiring structure and on a side surface of a portion of the dielectric masking layer adjacent to the opening, through the opening in the dielectric masking layer, with an upper portion of the via interconnect structure having exposed surfaces, wherein the selectively growing is performed while a top surface of the dielectric masking layer is exposed;
depositing a dielectric layer directly on both the exposed surfaces of the via interconnect structure and an upper surface of the dielectric masking layer;
forming an opening in the dielectric layer to expose an upper surface and a first portion of a sidewall of the via interconnect structure;
forming a barrier layer directly on the exposed upper surface and the first portion of the sidewall of the via interconnect structure after the dielectric layer is opened so that the exposed upper surface and the first portion of the sidewall of the via interconnect structure are covered with the barrier layer, and other portions of the sidewall of the via interconnect structure which are not exposed from the dielectric layer are devoid of the barrier layer; and
forming the upper wiring structure in the opening of the dielectric layer, the upper wiring structure being formed in electrical contact with the via interconnect structure directly on the barrier layer and extending over a plurality of surfaces of the via interconnect structure to increase a contact surface area between the upper wiring structure and the via interconnect structure to reduce an interfacial resistance between the upper wiring structure and the via interconnect structure, the upper wiring formed being aligned with a first side of the wiring structure and extending past a second side of the wiring structure,
wherein an interface between the via interconnect structure and the wiring structure is devoid of barrier material and/or liner material; and
wherein the wiring material and the barrier/liner material are separated by a boundary; and
wherein a first vertical wall of the barrier/liner material of the wiring structure is aligned with a first vertical wall of the barrier layer of the upper wiring structure and a second vertical wall of the of the barrier/liner material of the wiring structure is aligned with a second vertical wall of the barrier layer of the upper wiring structure.

11. The method of claim 10 , wherein the exposed portion of the wiring structure is cleaned to remove oxide by a hydrogen plasma process.

12. The

Assignees

• IBM

Inventors

• Backes Benjamin C
• Cohen Brian A
• Nag Joyeeta
• Radens Carl J

Classifications

• H10W20/4437

  the principal metal being a transition metal · CPC title

• H10W20/0693

  by forming self-aligned vias · CPC title

• H10P50/283

  by chemical means · CPC title

• H10P14/47

  Electrolytic deposition, i.e. electroplating; Electroless plating · CPC title

• H10W20/4441

  the principal metal being a refractory metal · CPC title