Self-aligned via interconnect structures

Patent metadata

Field	Value
Publication number	US-11348832-B2
Application number	US-201916460250-A
Country	US
Kind code	B2
Filing date	Jul 2, 2019
Priority date	Dec 8, 2014
Publication date	May 31, 2022
Grant date	May 31, 2022

Abstract

A self-aligned via interconnect structures and methods of manufacturing thereof are disclosed. The method includes forming a wiring structure in a dielectric material. The method further includes forming a cap layer over a surface of the wiring structure and the dielectric material. The method further includes forming an opening in the cap layer to expose a portion of the wiring structure. The method further includes selectively growing a metal or metal-alloy via interconnect structure material on the exposed portion of the wiring structure, through the opening in the cap layer. The method further includes forming an upper wiring structure in electrical contact with the metal or metal-alloy via interconnect structure.

First claim

What is claimed:

1. A method, comprising:
forming a trench in an interlevel dielectric material;
forming a wiring structure within the trench, comprising:
forming a barrier material on sidewalls of the trench;
forming a metal material in remaining portions of the trench, directly on the barrier material; and
removing any of the barrier material and metal material from an upper surface of the interlevel dielectric material, outside of the trench, the removing of the metal material also planarizes the wiring structure;

depositing a dielectric cap layer directly contacting and over both the wiring structure and interlevel dielectric material;
exposing a portion of the wiring structure by etching an opening in the dielectric cap such that the dielectric cap still remains over the barrier material on sidewalls of the trench and on at least one of side of the metal material of the wiring structure;
forming a self-aligned via interconnect structure in direct electrical contact with the metal material of the wiring structure by overfilling the opening with a metal using a metal growth process such that the metal directly contacts the wiring structure and the overfilling of the metal of the self-aligned via interconnect structure includes an overhang of metal which directly contacts a top surface of the dielectric cap;
depositing an interlevel dielectric material over the self-aligned via interconnect structure and the dielectric cap;
etching a trench within the interlevel dielectric material to expose multiple surfaces of the metal of the self-aligned via interconnect structure;
depositing a barrier material and liner material directly on sidewalls of the trench and on the multiple surfaces of the metal of the self-aligned via interconnect structure; and
electroplating another metal material on the liner material to form an upper wiring structure in electrical contact with the self-aligned via interconnect structure.

2. The method of claim 1 , wherein the metal growth process is a selective cobalt growth process which overfills the opening with cobalt.

3. The method of claim 2 , wherein the selective cobalt growth process laterally overgrows onto edges of the opening.

4. The method of claim 3 , wherein the selective cobalt growth process forms the self-aligned via interconnect structure onto a surface of the dielectric cap.

5. The method of claim 4 , wherein the self-aligned via interconnect structure is cobalt.

6. The method of claim 1 , wherein the upper wiring structure is formed to overlap at least one side of the self-aligned via interconnect structure.

7. The method of claim 1 , wherein the upper wiring structure is formed to overlap sides of the self-aligned via interconnect structure.

8. The method of claim 1 , wherein an interface between the self-aligned via interconnect structure and the wiring structure is devoid of the barrier material and liner material.

9. The method of claim 1 , wherein the etching of the trench within the interlevel dielectric material extends beyond an upper portion of the self-aligned via interconnect structure.

10. The method of claim 1 , wherein the depositing the dielectric cap comprises a deposition of a dielectric masking material.

11. The method of claim 1 , wherein the etching of the opening in the dielectric cap comprises forming a slot which exposes a portion of the wiring structure.

12. The method of claim 11 , wherein the slot is formed orthogonal to the wiring structure.

13. The method of claim 11 , wherein a contact region between the self-aligned via interconnect structure and a portion of the dielectric cap is devoid of the barrier material and liner material.

14. The method of claim 1 , wherein the multiple surfaces of the self-aligned via interconnect structure comprises a top surface and side surfaces.

15. The method of claim 1 , wherein the another metal is electroplated within the trench of the interlevel dielectric material.

16. The method of claim 15 , wherein the barrier and liner material are further formed on a surface of the interlevel dielectric material outside of the trench.

17. The method of claim 16 , further comprising removing the barrier and liner material and residue of the metal material from the surface of the interlevel dielectric material outside of the trench.

18. The method of claim 15 , wherein the metal material is formed in direct contact with the barrier material on the sidewalls of the trench and the multiple surfaces of the self-aligned via interconnect structure.

19. The method of claim 1 , wherein the overfilling of the metal of the self-aligned via interconnect structure comprises a lateral overgrowth of cobalt material onto edges of the opening and directly on the dielectric cap layer by “x” distance on one or both sides.

20. The method of claim 19 , wherein the “x” distance is equal to an overlap of the upper wiring structure in electrical contact with the self-aligned via interconnect structure.

Assignees

• IBM

Inventors

• Backes Benjamin C
• Cohen Brian A
• Nag Joyeeta
• Radens Carl J

Classifications

• H10W20/4437

  the principal metal being a transition metal · CPC title

• H10W20/0693

  by forming self-aligned vias · CPC title

• H10P50/283

  by chemical means · CPC title

• H10P14/47

  Electrolytic deposition, i.e. electroplating; Electroless plating · CPC title

• H10W20/4441

  the principal metal being a refractory metal · CPC title