Mitigating slow read disturb in a memory sub-system
US-2026064313-A1 · Mar 5, 2026 · US
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Puzzilli Giuseppina patents
Puzzilli Giuseppina is listed as an inventor on 67 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Puzzilli Giuseppina |
| Total patents | 67 |
| First publication | Jan 29, 2015 |
| Latest publication | Mar 5, 2026 |
Notable patents
Publications ranked by popularity score, then publication date.
Mitigating slow read disturb in a memory sub-system
US-12498877-B2 · Dec 16, 2025 · US
Partitioned memory having error detection capability
US-12026052-B2 · Jul 2, 2024 · US
Mitigating slow read disturb in a memory sub-system
US-2024184481-A1 · Jun 6, 2024 · US
Simultaneous statistical multi-subblock verify for nand memories
US-2024136002-A1 · Apr 25, 2024 · US
Deck reset read
US-2024127896-A1 · Apr 18, 2024 · US
Mitigating slow read disturb in a memory sub-system
US-11941285-B2 · Mar 26, 2024 · US
Implementing fault tolerant page stripes on low density memory systems
US-11899966-B2 · Feb 13, 2024 · US
Latent read disturb mitigation in memory devices
US-11847335-B2 · Dec 19, 2023 · US
Read calibration based on ranges of program/erase cycles
US-11797216-B2 · Oct 24, 2023 · US
Recent patents
Latest publications not already listed above.
Separate partition for buffer and snapshot memory
US-11789629-B2 · Oct 17, 2023 · US
Threshold voltage based on program/erase cycles
US-11776629-B2 · Oct 3, 2023 · US
Partitions within snapshot memory for buffer and snapshot memory
US-11775208-B2 · Oct 3, 2023 · US
Storing highly read data at low impact read disturb pages of a memory device
US-11762767-B2 · Sep 19, 2023 · US
Adjusting a preprogram voltage based on use of a memory device
US-11709616-B2 · Jul 25, 2023 · US
Read voltage calibration for copyback operation
US-11694763-B2 · Jul 4, 2023 · US
Read window based on program/erase cycles
US-11688479-B2 · Jun 27, 2023 · US
Threshold voltage distribution adjustment for buffer
US-11663104-B2 · May 30, 2023 · US
Partitioned memory having error detection capability
US-2023044883-A1 · Feb 9, 2023 · US
Data management during a copyback operation
US-11556267-B2 · Jan 17, 2023 · US
Adjusting a preprogram voltage based on use of a memory device
US-2022391125-A1 · Dec 8, 2022 · US
Implementing fault tolerant page stripes on low density memory systems
US-2022357873-A1 · Nov 10, 2022 · US
Read calibration based on ranges of program/erase cycles
US-2022350520-A1 · Nov 3, 2022 · US
Separate partition for buffer and snapshot memory
US-2022350517-A1 · Nov 3, 2022 · US
Trims corresponding to logical unit quantity
US-11487436-B2 · Nov 1, 2022 · US
Storing highly read data at low impact read disturb pages of a memory device
US-2022342813-A1 · Oct 27, 2022 · US
Partitioned memory having error detection capability
US-11481273-B2 · Oct 25, 2022 · US
Mitigating slow read disturb in a memory sub-system
US-2022334756-A1 · Oct 20, 2022 · US
Temperature-dependent operations in a memory device
US-11468949-B2 · Oct 11, 2022 · US
Adjusting a preprogram voltage based on use of a memory device
US-11461035-B2 · Oct 4, 2022 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Micron Technology Inc | 62 |
| Intel Corp | 2 |
| Intel NDTM US LLC | 2 |
| Lodestar Licensing Group Llc | 1 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G06F3/0679 | 36 |
| G11C16/10 | 23 |
| G06F3/0619 | 23 |
| G11C16/26 | 22 |
| G11C16/0483 | 21 |