Mitigating slow read disturb in a memory sub-system

Patent metadata

Field	Value
Publication number	US-11941285-B2
Application number	US-202117235216-A
Country	US
Kind code	B2
Filing date	Apr 20, 2021
Priority date	Apr 20, 2021
Publication date	Mar 26, 2024
Grant date	Mar 26, 2024

Abstract

Disclosed is a system that comprises a memory device and a processing device, operatively coupled with the memory device, to perform operations that include, receiving a read request to perform a read operation on a block of the memory device; determining whether an entry corresponding to the block is stored in a data structure associated with the memory device; responsive to the entry being stored in the data structure, incrementing a counter associated with the block to track a number of read operations performed on the block of the memory device; resetting a timer associated with the block to an initial value, wherein the timer is to track a period of time that elapses since the read operation was performed on the block of the memory device; determining that the counter and the timer satisfy a first criterion; and responsive to determining that the counter and the timer satisfy the first criterion, removing the entry corresponding to the block from the data structure associated with the memory device.

First claim

What is claimed is:

1. A system comprising:
a memory device; and
a processing device, operatively coupled with the memory device, to perform operations comprising:
receiving a read request to perform a read operation on a block of the memory device;
determining whether an entry corresponding to the block is stored in a data structure associated with the memory device;
responsive to the entry being stored in the data structure, incrementing a counter associated with the block to track a number of read operations performed on the block of the memory device;
resetting a timer associated with the block to an initial value, wherein the timer is to track a period of time that elapses since the read operation was performed on the block of the memory device;
determining that the counter and the timer satisfy a first criterion, wherein the first criterion corresponds to respective final values of the counter and the timer, and wherein satisfying the first criterion is indicative of a minimum number of read operations performed on the block; and
responsive to determining that the counter and the timer satisfy the first criterion, issuing a voltage discharge command to the block, wherein issuing the voltage discharge command results in the block reaching a ground voltage.

2. The system of claim 1 , wherein the counter and the timer are stored in the entry corresponding to the block in the data structure with the memory device.

3. The system of claim 1 , further comprising, responsive to determining that the counter and the timer satisfy the first criterion, removing the entry corresponding to the block from the data structure associated with the memory device.

4. The system of claim 3 , wherein removing the entry corresponding to the block from the data structure associated with the memory device is responsive to determining that the counter satisfies a second criterion.

5. The system of claim 1 , wherein determining that the counter and the timer satisfy a first criterion comprises determining that the counter and the timer have both reached the respective final values.

6. The system of claim 1 , wherein the timer is to count down from the initial value to the respective final value of the timer, and wherein the processing device to perform operations further comprising:
responsive to determining that the timer reaches the respective final value of the timer, decrementing the counter by a defined amount.

7. The system of claim 1 , wherein the processing device to perform operations further comprising:
responsive to the entry corresponding to the block not being stored in the data structure, removing an entry corresponding to another block from the data structure associated with the memory device and creating the entry corresponding to the block in the data structure.

8. A method comprising:
receiving a read request to perform a read operation on a block of a memory device;
determining that an entry corresponding to the block is stored in a data structure associated with the memory device;
responsive to the entry being stored in the data structure, incrementing a counter associated with the block to track a number of read operations performed on the block of the memory device;
resetting a timer associated with the block to an initial value, wherein the timer is to track a period of time that elapses since the read operation was performed on the block of the memory device;
determining that the counter and the timer satisfy a first criterion, wherein the first criterion corresponds to respective final values of the counter and the timer, and wherein satisfying the first criterion is indicative of a minimum number of read operations performed on the block; and
responsive to determining that the counter and the timer satisfy the first criterion, issuing a voltage discharge command to the block, wherein issuing the voltage discharge command results in the block reaching a ground voltage.

9. The method of claim 8 , wherein the counter and the timer are stored in the entry corresponding to the block in the data structure associated with the memory device.

10. The method of claim 8 , further comprising, responsive to determining that the counter and the timer satisfy the first criterion, removing the entry corresponding to the block from the data structure associated with the memory device.

11. The method of claim 10 , wherein removing the entry corresponding to the block from the data structure associated with the memory device is responsive to determining that the counter satisfies a second criterion.

12. The method of claim 8 , wherein determining that the counter and the timer satisfy a first criterion comprises determining that the counter and the timer have both reached the respective final values.

13. The method of claim 8 , wherein the timer is to count down from the initial value to the respective final value of the timer, and wherein, responsive to determining that the timer reaches the respective final value of the timer, decrementing the counter by a defined amount.

14. The method of claim 8 , further comprising:
responsive to the entry corresponding to the block not being stored in the data structure, removing an entry corresponding to another block from the data structure associated with the memory device and creating the entry corresponding to the block in the data structure.

15. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising:
receiving a series of read operation requests to perform read operations on a block of a memory device;
determining whether an entry corresponding to the block is stored in a data structure associated with the memory device;
responsive to the entry being stored in the data structure, incrementing a counter associated with the block to track a number of read operations performed on the block of the memory device;
resetting a timer associated with the block to an initial value, wherein the timer is to track a period of time that elapses since a read operation was performed on the block of the memory device;
identifying a trailing read from the series of read operation requests;
determining that the trailing read satisfies a first criterion, wherein the first criterion corresponds to respective final values of the counter and the timer associated with the block, and wherein satisfying the first criterion is indicative of a minimum number of read operations performed on the block; and
responsive to determining that the trailing read satisfies the first criterion, issuing a voltage discharge command to the block, wherein issuing the voltage discharge command results in the block reaching a ground voltage.

16. The non-transitory computer-readable storage medium of claim 15 , wherein identifying the trailing read from the series of read operation requests comprises:
determining that the counter and the timer satisfy the first criterion; and
responsive to determining that the counter and the timer satisfy the first criterion, removing the entry corresponding to the block from the data structure associated with the memory device.

17. The non-transitory computer-readable storage medium of claim 16 , wherein determining that the counter and the timer satisfy the first criterion comprises determining that the counter and the timer have both reached the respective final values.

18. The non-transitory computer-readable storage medium of claim 16 , wherein removing the entry corresponding to th

Assignees

• Micron Technology Inc

Inventors

• Rayaprolu Vamsi Pavan
• Muchherla Kishore Kumar
• Malshe Ashutosh
• Puzzilli Giuseppina
• Tehrani Saeed Sharifi

Classifications

• G06F3/0655 Primary

  Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices · CPC title

• G06F3/0604

  Improving or facilitating administration, e.g. storage management · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G11C7/22 Primary

  Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management · CPC title

• G06F3/061 Primary

  Improving I/O performance · CPC title