Latent read disturb mitigation in memory devices

Patent metadata

Field	Value
Publication number	US-11847335-B2
Application number	US-202117212437-A
Country	US
Kind code	B2
Filing date	Mar 25, 2021
Priority date	Mar 25, 2021
Publication date	Dec 19, 2023
Grant date	Dec 19, 2023

Abstract

A trigger condition associated with latent read disturb in a memory device is detected. In response to detecting the trigger condition associated with latent read disturb, one or more blocks in the memory device that are impacted by the trigger condition are placed in a stable state to mitigate latent read disturb in the one or more blocks.

First claim

What is claimed is:

1. A system comprising:
a memory device; and
a processing device, operatively coupled with the memory device, to perform operations comprising:
detecting a power state transition of a block of the memory device based on receiving, from the memory device, a signal indicating that the block is being placed in a low power state based on an anticipated idling of the block; and
in response to detecting the power state transition of the block, placing the block of the memory device in a stable state to mitigate latent read disturb in the block , the placing of the block in the stable state comprising sending a command to the memory device that causes the memory device to ground word lines in the block.

2. The system of claim 1 , wherein:
the block is a first block; and
the operations further comprise:
detecting a background scan being performed on a second block; and
placing the second block in a stable state in response to detecting the background scan being performed on the second block.

3. The system of claim 2 , wherein detecting the background scan being performed on the second block comprises detecting a background scan being performed on a page in the second block.

4. The system of claim 1 , wherein:
the block is a first block; and
the operations further comprise:
detecting an impending power down event at the memory device; and
placing a second block in a stable state in response to detecting the impending power down event.

5. The system of claim 4 , wherein:
the signal is a first signal;
the detecting of the impending power down even is based on receiving a second signal indicating that power down of the memory device is imminent.

6. The system of claim 1 , wherein the word lines in the block are floating prior to being grounded.

7. The system of claim 1 , wherein:
the memory device comprises a set of blocks; and
the placing of the block of the memory device in the stable state comprises placing the set of blocks in the stable state based on detecting the power state transition .

8. A method comprising:
detecting, by a processing device, a power state transition of a block of a memory device based on receiving, from the memory device, a signal indicating that the block is being placed in a low power state based on an anticipated idling of the block; and
in response to detecting the power state transition of the block, placing, by the processing device, the block of the memory device in a stable state to mitigate latent read disturb in the block , the placing of the block in the stable state comprising sending a command to the memory device that causes the memory device to ground word lines in the block .

9. The method of claim 8 , wherein:
the block is a first block; and
the method further comprises:
detecting a background scan being performed on a second block; and
placing the second block in a stable state in response to detecting the background scan being performed on the second block.

10. The method of claim 9 , wherein the detecting of the background scan being performed on the second block includes accessing error event data.

11. The method of claim 8 , wherein the word lines in the block are floating prior to being grounded.

12. The method of claim 8 , wherein the memory device grounds the word lines in the block in response to the command.

13. The method of claim 8 , wherein:
the memory device comprises a set of blocks; and
the placing of the block of the memory device in the stable state comprises placing the set of blocks in the stable state .

14. The method of claim 8 , wherein:
the memory device comprises a set of blocks; and
the placing of the block of the memory device in the stable state comprises placing a sub-set of blocks from the set of blocks in the stable state .

15. A computer-readable storage medium comprising instructions that, when executed by a processing device, configure the processing device to perform operations comprising:
detecting a power state transition of a block of a memory device based on receiving, from the memory device, a signal indicating that the block is being placed in a low power state based on an anticipated idling of the block; and
in response to detecting the power state transition of the block, placing the block in a stable state to mitigate latent read disturb in the block, the placing of the block in the stable state comprising sending a command to the memory device that causes the memory device to ground word lines in the block.

16. The computer-readable storage medium of claim 15 , wherein:
the block is a first block; and
the operations further comprise:
detecting a background scan being performed on a second block; and
placing the second block in a stable state in response to detecting the background scan being performed on the second block.

17. The computer-readable storage medium of claim 16 , wherein_the detecting of the background scan being performed on the second block includes accessing error event data.

18. The computer-readable storage medium of claim 15 , wherein the word lines in the block are floating prior to being grounded.

19. The computer-readable storage medium of claim 15 , wherein:
the memory device comprises a set of blocks; and
the placing of the block of the memory device in the stable state comprises placing the set of blocks in the stable state.

20. The computer-readable storage medium of claim 15 , wherein:
the memory device comprises a set of blocks; and
the placing of the block of the memory device in the stable state comprises placing a sub-set of blocks from the set of blocks in the stable state.

Assignees

• Micron Technology Inc

Inventors

• Shukla Pitamber
• Stoller Scott Anthony
• Righetti Niccolo'
• Puzzilli Giuseppina

Classifications

• G06F3/0647 Primary

  Migration mechanisms · CPC title

• G06F3/0604

  Improving or facilitating administration, e.g. storage management · CPC title

• G06F3/0625

  Power saving in storage systems · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G11C29/12 Primary

  Built-in arrangements for testing, e.g. built-in self testing [BIST] {or interconnection details} · CPC title