Temperature-dependent operations in a memory device

Patent metadata

Field	Value
Publication number	US-11468949-B2
Application number	US-202117200607-A
Country	US
Kind code	B2
Filing date	Mar 12, 2021
Priority date	Mar 12, 2021
Publication date	Oct 11, 2022
Grant date	Oct 11, 2022

Abstract

A method and system for temperature-dependent operations in a memory device are described. Temperature measurements of a memory device are recorded. A determination that a temperature measurement of the memory device satisfies a threshold temperature value is performed. In response to the determination, execution of a background operation in the memory device is delayed, and host system operation(s) continue to be executed in the memory device while execution of the background operation is delayed.

First claim

What is claimed is:

1. A method comprising:
recording one or more temperature measurements of a memory device;
determining that a temperature measurement of the memory device satisfies a threshold temperature value; and
in response to determining that the temperature measurement of the memory device satisfies the threshold temperature value, delaying execution of a background operation in the memory device, wherein one or more host system operations in the memory device continue to be executed while execution of the background operation is delayed.

2. The method of claim 1 , further comprising:
determining that another temperature measurement of the memory device does not satisfy the threshold temperature value; and
in response to determining that the other temperature of the memory device does not satisfy the threshold temperature value, resuming execution of the background operation.

3. The method of claim 1 , further comprising:
updating the threshold temperature value based on a plurality of recorded temperature measurements of the memory device.

4. The method of claim 1 , wherein the background operation is an erase operation.

5. The method of claim 1 , wherein the background operation is a program operation.

6. The method of claim 1 , wherein the background operation is part of a garbage collection process.

7. The method of claim 1 , wherein the background operation is part of a process for reconfiguration of a portion of memory from a first memory cell bit density to a second memory cell bit density.

8. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to:
record one or more temperature measurements of a memory device;
determine that a temperature measurement of the memory device satisfies a threshold temperature value; and
in response to determining that the temperature measurement of the memory device satisfies the threshold temperature value, delay execution of a background operation in the memory device, wherein one or more host system operations in the memory device continue to be executed while execution of the background operation is delayed.

9. The non-transitory computer-readable storage medium of claim 8 , wherein the processing device is further to:
determine that another temperature measurement of the memory device does not satisfy the threshold temperature value; and
in response to determining that the other temperature of the memory device does not satisfy the threshold temperature value, resume execution of the background operation.

10. The non-transitory computer-readable storage medium of claim 8 , wherein the processing device is further to:
update the threshold temperature value based on a plurality of recorded temperature measurements of the memory device.

11. The non-transitory computer-readable storage medium of claim 8 , wherein the background operation is an erase operation.

12. The non-transitory computer-readable storage medium of claim 8 , wherein the background operation is a program operation.

13. The non-transitory computer-readable storage medium of claim 8 , wherein the background operation is part of a garbage collection process.

14. The non-transitory computer-readable storage medium of claim 8 , wherein the background operation is part of a process for reconfiguration of a portion of memory from a first memory cell bit density to a second memory cell bit density.

15. A system comprising:
a memory device; and
a processing device, operatively coupled with the memory device, to:
record one or more temperature measurements of a memory device;
determine that a temperature measurement of the memory device satisfies a threshold temperature value;
in response to determining that the temperature measurement of the memory device satisfies the threshold temperature value, delay execution of a background operation in the memory device, wherein one or more host system operations in the memory device continue to be executed while execution of the background operation is delayed;
determine that another temperature measurement of the memory device does not satisfy the threshold temperature value; and
in response to determining that the other temperature of the memory device does not satisfy the threshold temperature value, resume execution of the background operation.

16. The system of claim 15 , wherein the processing device is further to:
update the threshold temperature value based on a plurality of recorded temperature measurements of the memory device.

17. The system of claim 15 , wherein the background operation is an erase operation.

18. The system of claim 15 , wherein the background operation is a program operation.

19. The system of claim 15 , wherein the background operation is part of a garbage collection process.

20. The system of claim 15 , wherein the background operation is part of a process for reconfiguration of a portion of memory from a first memory cell bit density to a second memory cell bit density.

Assignees

• Micron Technology Inc

Inventors

• Shukla Pitamber
• Puzzilli Giuseppina
• Righetti Niccolo′
• Stoller Scott A
• Venkataraman Priya

Classifications

• G06F11/3089

  Monitoring arrangements determined by the means or processing involved in sensing the monitored data, e.g. interfaces, connectors, sensors, probes, agents (software debugging using additional hardware using a specific debug interface G06F11/3656; performance evaluation by tracing or monitoring G06F11/3466) · CPC title

• G06F11/3058 Primary

  Monitoring arrangements for monitoring environmental properties or parameters of the computing system or of the computing system component, e.g. monitoring of power, currents, temperature, humidity, position, vibrations (thermal management in cooling arrangements of a computing system G06F1/206) · CPC title

• G06F11/3037

  where the computing system component is a memory, e.g. virtual memory, cache (accessing, addressing or allocating within memory systems or architectures G06F12/00; checking stores for correct operation G11C29/00) · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/32 Primary

  Timing circuits · CPC title