Deck reset read

Patent metadata

Field	Value
Publication number	US-2024127896-A1
Application number	US-202318395538-A
Country	US
Kind code	A1
Filing date	Dec 23, 2023
Priority date	Dec 23, 2023
Publication date	Apr 18, 2024
Grant date	—

Abstract

A storage device includes a storage array having multiple decks of NAND cells in a three dimensional (3D) stack. There can be any number of decks that have multiple wordlines in vertical stacks. The decks include a first deck and a second deck. Bias circuitry can apply different voltages to different decks of the storage array. The bias circuitry can apply a low bias to the first deck, with a first voltage low enough to not turn on the NAND cells of the first deck, and simultaneously apply a high bias to the second deck, with a second voltage high enough to turn on the NAND cells of the second deck.

First claim

What is claimed is:

1 . A storage device comprising:
multiple decks of three dimensional (3D) NAND cells, the multiple decks including a first deck and a second deck, each of the multiple decks having multiple wordlines stacked vertically; and bias circuitry to apply a low bias to the first deck, with a first voltage low enough to not turn on the NAND cells of the first deck, and simultaneously apply a high bias to the second deck, with a second voltage high enough to turn on the NAND cells of the second deck.

2 . The storage device of claim 1 , wherein the bias circuitry is to apply the low bias to the first deck and the high bias to the second deck based on timing.

3 . The storage device of claim 2 , wherein the timing comprises after application of a weak erase pulse (WEP).

4 . The storage device of claim 2 , wherein the timing comprises after bringing the storage device up from a suspend state.

5 . The storage device of claim 2 , wherein the timing comprises after bringing the storage device up from an idle state.

6 . The storage device of claim 1 , wherein the bias circuitry is to apply the low bias to the first deck to select the first deck for excess pillar holes, and is to apply the high bias to the second deck to deselect the second deck from having excess pillar holes.

7 . The storage device of claim 6 , wherein selection and deselection are based on a storage policy for the storage device.

8 . The storage device of claim 6 , wherein selection and deselection are based on a temperature of the storage device.

9 . The storage device of claim 6 , wherein selection and deselection are based on an architecture of the 3D NAND cells.

10 . A system comprising:
a processor device; and a storage device coupled to the processor device, the storage device including
multiple decks of three dimensional (3D) NAND cells, the multiple decks including a first deck and a second deck, each of the multiple decks having multiple wordlines stacked vertically; and
bias circuitry to apply a low bias to the first deck, with a first voltage low enough to not turn on the NAND cells of the first deck, and simultaneously apply a high bias to the second deck, with a second voltage high enough to turn on the NAND cells of the second deck.

11 . The system of claim 10 , wherein the bias circuitry is to apply the low bias to the first deck and the high bias to the second deck based on timing.

12 . The system of claim 11 , wherein the timing comprises after application of a weak erase pulse (WEP).

13 . The system of claim 11 , wherein the timing comprises after bringing the storage device up from a suspend state.

14 . The system of claim 11 , wherein the timing comprises after bringing the storage device up from an idle state.

15 . The system of claim 10 , wherein the bias circuitry is to apply the low bias to the first deck to select the first deck for excess pillar holes, and is to apply the high bias to the second deck to deselect the second deck from having excess pillar holes.

16 . The system of claim 15 , wherein selection and deselection are based on a storage policy for the storage device.

17 . The system of claim 15 , wherein selection and deselection are based on a temperature of the storage device.

18 . The system of claim 15 , wherein selection and deselection are based on an architecture of the 3D NAND cells.

19 . The system of claim 10 ,
wherein the processor device comprises a multicore processor; further comprising a display communicatively coupled to the processor device; further comprising a battery to power the system; or further comprising a network interface circuit to couple with a remote device over a network connection.

Assignees

• Intel NDTM US LLC

Inventors

• Zhang Chao
• Sun Xin
• Fastow Richard
• Puzzilli Giuseppina
• Parat Krishna K

Classifications

• G11C16/3427 Primary

  Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/08 Primary

  Address circuits; Decoders; Word-line control circuits · CPC title

• G11C16/16

  for erasing blocks, e.g. arrays, words, groups · CPC title

• G11C16/32

  Timing circuits · CPC title