Memory with hybrid write assist scheme
US-12512151-B1 · Dec 30, 2025 · US
This page is not indexed by search engines while we improve data quality.
Pilo Harold patents
Pilo Harold is listed as an inventor on 48 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Pilo Harold |
| Total patents | 48 |
| First publication | Apr 23, 2015 |
| Latest publication | Dec 30, 2025 |
Notable patents
Publications ranked by popularity score, then publication date.
Memory with external clock synchronized operation
US-12361990-B1 · Jul 15, 2025 · US
Interface level-shifter dual-rail memory architecture
US-12340864-B2 · Jun 24, 2025 · US
Reduced circuit area memory device with a half-word memory architecture
US-12340865-B2 · Jun 24, 2025 · US
Pseudo-2-port memory with dual pre-charge circuits
US-12308091-B2 · May 20, 2025 · US
Output driver level-shifting latch circuit for dual-rail memory
US-12243581-B1 · Mar 4, 2025 · US
SRAM non-clamping write driver with write assist
US-12165738-B2 · Dec 10, 2024 · US
At-speed synchronous write-through operation for testing two-port memory
US-12148490-B1 · Nov 19, 2024 · US
Reduced circuit area memory device with a half-word memory architecture
US-2024371416-A1 · Nov 7, 2024 · US
Scan chain compression for testing memory of a system on a chip
US-12112818-B2 · Oct 8, 2024 · US
Recent patents
Latest publications not already listed above.
Power supply tracking circuitry for embedded memories
US-12094513-B2 · Sep 17, 2024 · US
Memory clock level-shifting buffer with extended range
US-12073876-B2 · Aug 27, 2024 · US
Memory clock level-shifting buffer with extended range
US-2024062810-A1 · Feb 22, 2024 · US
Interface level-shifter dual-rail memory architecture
US-2023260555-A1 · Aug 17, 2023 · US
SRAM Non-Clamping Write Driver with Write Assist
US-2023206970-A1 · Jun 29, 2023 · US
Power supply tracking circuitry for embedded memories
US-2023125268-A1 · Apr 27, 2023 · US
Scan chain compression for testing memory of a system on a chip
US-2023005562-A1 · Jan 5, 2023 · US
Pseudo-2-port memory with dual pre-charge circuits
US-2022208239-A1 · Jun 30, 2022 · US
Memory bypass function for a memory
US-11017873-B2 · May 25, 2021 · US
Method and apparatus for memory noise-free wake-up protocol from power-down
US-10971218-B2 · Apr 6, 2021 · US
Method and Apparatus for Memory Noise-Free Wake-Up Protocol from Power-Down
US-2020381042-A1 · Dec 3, 2020 · US
Memory Bypass Function For A Memory
US-2020234784-A1 · Jul 23, 2020 · US
Method and apparatus for integrated level-shifter and memory clock
US-10706916-B1 · Jul 7, 2020 · US
Memory bypass function for a memory
US-10650906-B2 · May 12, 2020 · US
Overvoltage protection for a fine grained negative wordline scheme
US-10636457-B2 · Apr 28, 2020 · US
Overvoltage protection for a fine grained negative wordline scheme
US-2019259427-A1 · Aug 22, 2019 · US
Overvoltage protection for a fine grained negative wordline scheme
US-10381052-B2 · Aug 13, 2019 · US
Overvoltage protection for a fine grained negative wordline scheme
US-2018174645-A1 · Jun 21, 2018 · US
Overvoltage protection for a fine grained negative wordline scheme
US-9953698-B2 · Apr 24, 2018 · US
Overvoltage protection for a fine grained negative wordline scheme
US-2018068711-A1 · Mar 8, 2018 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Synopsys Inc | 24 |
| IBM | 23 |
| Globalfoundries Inc | 2 |
| Synopsis Inc | 1 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G11C11/417 | 28 |
| G11C11/418 | 20 |
| G11C5/147 | 19 |
| G11C5/14 | 19 |
| G11C8/08 | 17 |