Memory clock level-shifting buffer with extended range

Patent metadata

Field	Value
Publication number	US-12073876-B2
Application number	US-202217891395-A
Country	US
Kind code	B2
Filing date	Aug 19, 2022
Priority date	Aug 19, 2022
Publication date	Aug 27, 2024
Grant date	Aug 27, 2024

Abstract

A level shifter circuit includes a level shifter configured to receive a first clock signal associated with a first power level and generate a second clock signal associated with a second power level, wherein the second power level is greater than the first power level. The level shifter circuit further includes an input clock buffer having a first input, wherein the first input comprises the second clock signal from the level shifter, and a second input coupled in parallel to the first input, wherein the second input includes the first clock signal.

First claim

What is claimed is:

1. A level shifter circuit, comprising:
a level shifter configured to receive a first clock signal associated with a first power level (VDDP) and generate a second clock signal associated with a second power level (VDDA), wherein the second power level is greater than the first power level; and
an input clock buffer comprising a first input, wherein the first input comprises the second clock signal from the level shifter, and a second input coupled in parallel to the first input, wherein the second input comprises the first clock signal.

2. The level shifter circuit of claim 1 , wherein the first power level comprises a peripheral voltage and the second power level comprises a bitcell array voltage.

3. The level shifter circuit of claim 1 , wherein the input clock buffer is configured to generate an output clock signal when a difference between the second power level and the first power level is above a determined threshold voltage, and generate the output clock signal when the difference between the second power level and the first power level is below the determined threshold voltage.

4. The level shifter circuit of claim 3 , wherein the output clock signal is provided as inputs to a memory periphery and a memory timer, wherein the memory periphery and memory timer are coupled in parallel to the input clock buffer.

5. The level shifter circuit of claim 4 , wherein the input clock buffer comprises a third input, wherein the third input is received from the memory timer in parallel to the first input and the second input.

6. The level shifter circuit of claim 3 , wherein the output clock signal comprises an internal memory clock signal.

7. The level shifter circuit of claim 1 , wherein the integrated circuit comprises a single rail design or a dual rail design.

8. The level shifter circuit of claim 1 , wherein an input terminal of the level shifter is coupled to an input/output circuit.

9. A method for level-shifting in an integrated circuit, the method comprising:
providing a level shifter to receive a first clock signal associated with a first power level and generate a second clock signal associated with a second power level, wherein the second power level is greater than the first power level;
providing an input clock buffer with a first input, wherein the first input comprises the second clock signal from the level shifter; and
providing the input clock buffer with a second input in parallel to the first input, wherein the second input comprises the first clock signal.

10. The method of claim 9 , wherein the first power level comprises a peripheral voltage and the second power level comprises a bitcell array voltage.

11. The method of claim 9 , further comprising:
generating an output clock signal, by the input clock buffer, when a difference between the second power level and the first power level is above a determined threshold voltage; and
generating the output clock signal when the difference between the second power level and the first power level is below the determined threshold voltage.

12. The method of claim 11 , further comprising:
providing the output clock signal as inputs to a memory periphery and a memory timer, wherein the memory periphery and memory timer are coupled in parallel to the input clock buffer.

13. The method of claim 12 , further comprising:
providing the input clock buffer with a third input, wherein the third input is received from the memory timer in parallel to the first input and the second input.

14. The method of claim 11 , wherein the output clock signal comprises an internal memory clock signal.

15. The method of claim 9 , wherein the integrated circuit comprises a single rail design or a dual rail design.

16. The method of claim 9 , further comprising:
coupling an input terminal of the level shifter to an input/output circuit.

17. A non-transitory computer readable medium comprising instructions which when executed by a processing device, cause the processing device to generate a digital representation of a level-shifting circuit, the level-shifting circuit comprising:
a level shifter configured to receive a first clock signal associated with a first power level (VDDP) and generate a second clock signal associated with a second power level (VDDA), wherein the second power level is greater than the first power level; and
an input clock buffer comprising a first input, wherein the first input comprises the second clock signal from the level shifter, and a second input coupled in parallel to the first input, wherein the second input comprises the first clock signal.

18. The non-transitory computer readable medium of claim 17 , wherein the first power level comprises a peripheral voltage and the second power level comprises a bitcell array voltage.

19. The non-transitory computer readable medium of claim 17 , wherein the input clock buffer is configured to generate an output clock signal when a difference between the second power level and the first power level is above a determined threshold voltage, and generate the output clock signal when the difference between the second power level and the first power level is below the determined threshold voltage.

20. The non-transitory computer readable medium of claim 19 , wherein the output clock signal is provided as inputs to a memory periphery and a memory timer, wherein the memory periphery and memory timer are coupled in parallel to the input clock buffer.

Assignees

• Synopsys Inc

Inventors

• Pilo Harold

Classifications

• G11C11/417

  for memory cells of the field-effect type · CPC title

• G11C5/147

  Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops (G11C5/141 takes precedence) · CPC title

• G11C7/1057

  Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load · CPC title

• G11C7/1084

  Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load · CPC title

• G11C11/418 Primary

  Address circuits · CPC title