Overvoltage protection for a fine grained negative wordline scheme

Patent metadata

Field	Value
Publication number	US-9953698-B2
Application number	US-201715797068-A
Country	US
Kind code	B2
Filing date	Oct 30, 2017
Priority date	Aug 4, 2014
Publication date	Apr 24, 2018
Grant date	Apr 24, 2018

Abstract

A fine grained negative wordline scheme for SRAM memories is disclosed. The scheme includes a circuit having a static random access memory (SRAM) cell including at least a wordline coupled to a plurality of NFETs of a transistor array. The circuit further includes a wordline driver including a plurality of inverters coupled between a wordline group decode node, a power supply and the wordline. Overvoltage on the wordline driver and NFETs of the SRAM cell are eliminated by applying a power gating mode and lowering the power supply voltage.

First claim

What is claimed is:

1. A method comprising providing a negative voltage to a wordline of an SRAM cell during a power gating mode, wherein the negative voltage is passed through an NFET of an inverter of a wordline driver, to eliminate an overvoltage on an NFET device coupled to the wordline of the SRAM, and allowing or preventing the negative voltage from passing to a node of a wordline pulldown network coupled to the NFET of the inverter by a first control device in the wordline pulldown network, wherein the wordline pulldown network is coupled to a wordline group decode node to control operation of the first control device of the wordline pulldown network for allowing or preventing the negative voltage from passing to the node of the wordline pulldown network.

2. The method of claim 1 , further comprising passing 0 or higher voltage to the wordline of the SRAM cell during a powering up state.

3. The method of claim 1 , wherein the negative voltage is applied only to the wordline when a positive supply voltage is lowered.

4. The method of claim 1 , wherein the negative voltage is applied only to the wordline when power gating is turned on.

5. The method of claim 4 , wherein, when the power gating is turned off, the negative voltage is replaced with a GND (0V) signal.

6. The method of claim 5 , further comprising allowing or preventing the GND (0V) signal from passing to the node of the wordline pulldown network by a second control device in the wordline pulldown network.

7. The method of claim 6 , wherein the first control device comprises a first NFET device of the wordline pulldown network.

8. The method of claim 7 , wherein the second control device comprises a second NFET device of the wordline pulldown network.

9. The method of claim 1 , wherein a gate of the NFET device of the SRAM is coupled to the wordline to receive the negative voltage from the wordline driver.

10. The method of claim 6 , wherein control terminals of the first control device and the second control device are both coupled to be controlled by the wordline group decode node.

11. The method of claim 10 , wherein the control terminal of the first control device is coupled directly to the wordline group decode node and the control terminal of the second control device is coupled to the wordline group decode node through an inverter.

12. The method of claim 11 , wherein the first control device comprises a first NFET device of the wordline pulldown network the second control device comprises a second NFET device of the wordline pulldown network.

13. The method of claim 1 , wherein the word line driver and the SRAM are coupled to a power gating voltage circuit.

14. The method of claim 13 , wherein the power gating voltage circuit is comprised of an FET including a source-drain path for connecting the word line driver and the SRAM to a power supply line.

15. The method of claim 14 , wherein a control gate of the FET of the power gating voltage circuit is coupled to the word line group decode node.

16. The method of claim 14 , wherein the FET of the power gating voltage circuit is a PFET.

Assignees

• IBM

Inventors

• Pilo Harold
• Wu Richard S

Classifications

• G11C11/417 Primary

  for memory cells of the field-effect type · CPC title

• G11C5/14

  Power supply arrangements {, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels} · CPC title

• G11C11/418

  Address circuits · CPC title

• G11C5/147 Primary

  Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops (G11C5/141 takes precedence) · CPC title

• G11C8/08

  Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines · CPC title