Memory with external clock synchronized operation

Patent metadata

Field	Value
Publication number	US-12361990-B1
Application number	US-202318370773-A
Country	US
Kind code	B1
Filing date	Sep 20, 2023
Priority date	Sep 20, 2023
Publication date	Jul 15, 2025
Grant date	Jul 15, 2025

Abstract

A method and system are provided for controlling clock operation in a memory that applies a test mode to test functionality of the memory which controls timing in a self-time loop using an external clock that on a rising edge triggers a main clock and on a falling edge provides a reset timer return path to reset the main clock signal. In the reset timer return path, a rising edge of the external clock triggers start of a self-time loop, and the rising edge of the external clock also controls the reset timer return path to block generation of a reference bit line (RBL) signal. In the reset timer return path, a falling edge of the external clock generates the RBL signal to provide an external clock return signal to enable an end of cycle for the self-time loop.

First claim

What is claimed is:

1. A memory clock control circuit comprising:
an internal clock generation circuit comprising:
a main clock latch having a first input receiving an external clock signal CLK and an output providing a main clock signal MCLKB; and
a reset latch having a first input receiving the external clock signal CLK and a second input for receiving a main clock return MCLKB_RET signal, and providing an output that resets the main clock latch; and

a timer control circuit comprising:
a first logic gate having a first input receiving the external clock signal CLK through a buffer as a test clock signal T 1 CLK, a second input receiving a test clock signal TEST_CLK and having an output;
a second logic gate having a first input receiving the output of the first logic gate and a second input receiving the main clock signal MCLKB from the main clock latch and providing an output;
a reference bit line (RBL) providing gate having (i) a power control input receiving the test clock signal T 1 CLK, (ii) an input coupled to the output of the second logic gate and (iii) providing an output according to which the main clock return MCLKB_RET signal is provided to the second input of the reset latch of the internal clock generation circuit; and
a bypass providing the test clock signal T 1 CLK from the first input of the first logic gate to the RBL providing gate, wherein the RBL providing gate is (i) disabled on a rising edge of the test clock signal T 1 CLK and (ii) enabled on a falling edge of the test clock signal T 1 CLK.

2. The memory clock control circuit of claim 1 ,
wherein the timer control circuit receives a reference bitline read cycle signal RBLRD and a reference bitline write cycle signal RBLWR, and
wherein the reference bitline read cycle signal RBLRD and the reference bitline write cycle signal RBLWR are provided together to the RBL providing gate as controlled by the output of the second logic gate.

3. The memory clock control circuit of claim 2 ,
wherein the timer control circuit further includes a buffer having an input connected to the output of the RBL providing gate and having an output according to which the main clock return MCLKB_RET signal is provided to the second input of the reset latch,
wherein the output of the buffer provides a stop clock STCLK signal, and
wherein the memory clock control circuit further comprises:
a column decode clock signal generator having an output controlled by the stop clock STCLK signal and the main clock signal MCLKB, and
a wordline decode clock signal generator having an output controlled by the stop clock STCLK signal and the main clock signal MCLKB.

4. The memory clock control circuit of claim 3 ,
wherein the output from the buffer is inverted to provide an inverse of the stop clock signal LOFF, and
wherein the memory clock control circuit further comprises:
a sense amplifier timing generator circuit having an output controlled by the inverse of the stop clock signal LOFF, the stop clock STCLK signal and the main clock signal MCLKB; and
a bitline restore timing signal generator circuit having an output controlled by the inverse of the stop clock signal LOFF and the main clock signal MCLKB.

5. The memory clock control circuit of claim 1 ,
wherein the timer control circuit receives a reference bitline read cycle signal RBLRD, which is provided to the RBL providing gate,
wherein a read data enable (RD) signal is provided that enables the reference bitline read cycle signal RBLRD to be provided to the RBL providing gate,
wherein the timer control circuit receives a reference bitline write cycle signal RBLWR that is driven by the main clock signal MCLKB,
wherein an inverse of the RD signal (RDB) is provided that enables the reference bitline write cycle signal RBLWR to be provided,
wherein the memory clock control circuit further comprises a second RBL providing gate having a first input receiving the output of the RBL providing gate, and a second input receiving the reference bitline write cycle signal RBLWR, and
wherein an output the second RBL providing gate provides and RBL signal according to which the main clock return MCLKB_RET signal is generated.

6. The memory clock control circuit of claim 5 ,
wherein the timer control circuit further includes a buffer having an input connected to the output of the second RBL providing gate and having an output providing the main clock return MCLKB_RET signal connected to the second input of the reset latch,
wherein the input of the buffer provides a stop clock STCLK signal, and
wherein the memory clock control circuit further comprises:
a column decode clock signal generator having an output controlled by the stop clock STCLK signal and the main clock signal MCLKB, and
a wordline decode clock signal generator having an output controlled by the stop clock STCLK signal and the main clock signal MCLKB.

7. The memory clock control circuit of claim 6 ,
wherein the input to the buffer is further buffered to provide an inverse of the stop clock signal LOFF, and
wherein the memory clock control circuit further comprises:
a sense amplifier timing generator circuit having an output controlled by the inverse of the stop clock signal LOFF, the stop clock STCLK signal and the main clock signal MCLKB; and
a bitline restore timing signal generator circuit having an output controlled by the inverse of the stop clock signal LOFF and the main clock signal MCLKB.

8. The memory clock control circuit of claim 1 , wherein the first logic gate is a first NOR gate and the second logic gate is a second NOR gate.

9. A method for controlling clock operation in a memory, the method comprising:
applying a test mode which controls timing using an external clock to test functionality of the memory; and
providing a reset timer return path from the timer control circuit to the internal clock generation circuit to reset a main clock signal (MCLKB) stored in the internal clock generation circuit, the reset timer return path providing, during the test mode, a main clock return (MCLKB_RET) signal to the internal clock generation circuit in dependence on the external clock, wherein a rising edge of the external clock triggers start of a self-time loop during which the main clock signal MCLKB is set and then reset,
wherein the rising edge of the external clock controls setting of the main clock signal MCLKB and enables the reset timer return path to block generation of a reference bit line (RBL) signal to prevent generation of the main clock return signal MCLKB until the falling edge of the external clock, and
wherein a falling edge of the external clock causes a generation of a reference bit line (RBL) signal, on the reset timer return path, to provide the main clock return MCLKB_RET signal to enable an end of cycle for the self-time loop.

10. The method of claim 9 , wherein the falling edge of the external clock controls a timing launch for memory circuit components comprising:
triggering a sense amplifier enable (SAE);
shutting off a column line decode;
shutting off a wordline decode; and
triggering a bitline restore.

11. The method of claim 10 , wherein the triggering of the sense amplifier enable (SAE) clock in the test mode matches the triggering of the sense amplifier enable (SAE) clock in a functional mode.

12. The method of claim 9 , wherein the falling edge of the external clock controls a timing launch of memory circuit components comprising:
shutting off a column line decode; and
shutting off a wordline decode,
wherein the shutting off of the column line decode and the shutting off of the wordline decode is performed before the providing of the m

Assignees

• Synopsys Inc

Inventors

• Pilo Harold
• Kainth Sanjiv
• Garg Anurag

Classifications

• G11C7/06

  Sense amplifiers; Associated circuits {, e.g. timing or triggering circuits} · CPC title

• G11C8/18

  Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals · CPC title

• G11C7/222 Primary

  Clock generating, synchronizing or distributing circuits within memory device · CPC title

• G11C8/10

  Decoders · CPC title

• H03K19/20

  characterised by logic function, e.g. AND, OR, NOR, NOT circuits (H03K19/003 - H03K19/01 take precedence) · CPC title